[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Dmitrii Petrov via Phabricator via cfe-commits]

dnpetrov-sc updated this revision to Diff 480352.
dnpetrov-sc edited the summary of this revision.
dnpetrov-sc added a comment.

- fixed new line at end-of-file in RISCVSchedSCR1.td;
- dropped scr1-min (RV32E unsupported).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSCR1.td

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