[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedSCR1.td:208
+}
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Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302