[PATCH] D123450: [clang-format] Parse Verilog if statements

[Owen Pan via Phabricator via cfe-commits]

owenpan added inline comments.


================
Comment at: clang/lib/Format/FormatToken.h:1572
+  bool isBlockBegin(const FormatToken &Tok, const FormatStyle &Style) const {
+    return Style.isVerilog() ? isVerilogBegin(Tok) : Tok.is(tok::l_brace);
+  }
----------------
HazardyKnusperkeks wrote:
> Shouldn't we add TT_MacroBlockBegin?
Adding `TT_MacroBlockBegin` here caused an [[ https://github.com/llvm/llvm-project/issues/59335 | assertion failure ]]. See also D123450#3768367.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123450/new/

https://reviews.llvm.org/D123450