[clang] 482b8b4 - [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

via cfe-commits cfe-commits at lists.llvm.org
Wed Nov 30 08:36:00 PST 2022


Author: eopXD
Date: 2022-11-30T08:35:53-08:00
New Revision: 482b8b493be099c2f70d4b2edd60041c403a247f

URL: https://github.com/llvm/llvm-project/commit/482b8b493be099c2f70d4b2edd60041c403a247f
DIFF: https://github.com/llvm/llvm-project/commit/482b8b493be099c2f70d4b2edd60041c403a247f.diff

LOG: [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

According to version_macro.adoc under rvv-intrinsic-doc, the compiler
should have a macro to imply such availability.

Link: https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/version_macro.adoc

Reviewed By: kito-cheng, asb

Differential Revision: https://reviews.llvm.org/D138930

Added: 
    

Modified: 
    clang/lib/Basic/Targets/RISCV.cpp
    clang/test/Preprocessor/riscv-target-features.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index f6db5b8aaf45d..4dc96a193094e 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -190,8 +190,12 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (ISAInfo->hasExtension("c"))
     Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x")) {
     Builder.defineMacro("__riscv_vector");
+    // Currently we support the v0.10 RISC-V V intrinsics
+    unsigned Version = (0 * 1000000) + (10 * 1000);
+    Builder.defineMacro("__riscv_v_intrinsic", Twine(Version));
+  }
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {

diff  --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index c01e4b15f07be..8884b0989086d 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -26,6 +26,7 @@
 // CHECK-NOT: __riscv_zfh
 // CHECK-NOT: __riscv_v
 // CHECK-NOT: __riscv_vector
+// CHECK-NOT: __riscv_v_intrinsic
 // CHECK-NOT: __riscv_zbkc
 // CHECK-NOT: __riscv_zbkx
 // CHECK-NOT: __riscv_zbkb
@@ -262,6 +263,7 @@
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64D-EXT %s
 // CHECK-ZVE64D-EXT: __riscv_v_elen 64
 // CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64
+// CHECK-ZVE64D-EXT: __riscv_v_intrinsic 10000{{$}}
 // CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64D-EXT: __riscv_vector 1
 // CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}}
@@ -275,6 +277,7 @@
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64F-EXT %s
 // CHECK-ZVE64F-EXT: __riscv_v_elen 64
 // CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32
+// CHECK-ZVE64F-EXT: __riscv_v_intrinsic 10000{{$}}
 // CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64F-EXT: __riscv_vector 1
 // CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}}
@@ -287,6 +290,7 @@
 // RUN: | FileCheck --check-prefix=CHECK-ZVE64X-EXT %s
 // CHECK-ZVE64X-EXT: __riscv_v_elen 64
 // CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0
+// CHECK-ZVE64X-EXT: __riscv_v_intrinsic 10000{{$}}
 // CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64X-EXT: __riscv_vector 1
 // CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}}
@@ -297,6 +301,7 @@
 // RUN: | FileCheck --check-prefix=CHECK-ZVE32F-EXT %s
 // CHECK-ZVE32F-EXT: __riscv_v_elen 32
 // CHECK-ZVE32F-EXT: __riscv_v_elen_fp 32
+// CHECK-ZVE32F-EXT: __riscv_v_intrinsic 10000{{$}}
 // CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32F-EXT: __riscv_vector 1
 // CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}}
@@ -307,6 +312,7 @@
 // RUN: | FileCheck --check-prefix=CHECK-ZVE32X-EXT %s
 // CHECK-ZVE32X-EXT: __riscv_v_elen 32
 // CHECK-ZVE32X-EXT: __riscv_v_elen_fp 0
+// CHECK-ZVE32X-EXT: __riscv_v_intrinsic 10000{{$}}
 // CHECK-ZVE32X-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32X-EXT: __riscv_vector 1
 // CHECK-ZVE32X-EXT: __riscv_zve32x 1000000{{$}}


        


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