[PATCH] D138579: [AArch64] Assembly support for FEAT_LRCPC3

[Sam Elliott via Phabricator via cfe-commits]

lenary accepted this revision.
lenary added a comment.
This revision is now accepted and ready to land.

Some comment nits that you can fixup on commit.



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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:3913
+// are post-indexed, and the immediate values are not inside the [] brackets and
+// thus not verified by GPR64sp0 parser.
+def STLRW0  : InstAlias<"stlr\t$Rt, [$Rn, #0]" , (STLRW   GPR32: $Rt, GPR64sp:$Rn)>;
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Maybe?

Maybe also clarify that `GPR64sp0` is not appropriate because it parses and discards the optional zero.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:8556
+  //                                           size   opc    opc2
+  def STILPwo : BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$Rn_wb)                       , (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp" , "\t$Rt, $Rt2, [$Rn, #-8]!",  "$Rn = $Rn_wb">; /* PUSH register pair */
+  def STILPxo : BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$Rn_wb)                       , (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp" , "\t$Rt, $Rt2, [$Rn, #-16]!", "$Rn = $Rn_wb">; /* PUSH register pair */
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nit: Please remove this comment, it doesn't correspond to anything in the spec, and I don't think it's helpful.


Repository:
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  https://reviews.llvm.org/D138579/new/

https://reviews.llvm.org/D138579