[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Philip Reames via Phabricator via cfe-commits]

reames created this revision.
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This change provides an implementation of the XVentanaCondOps vendor extension.  This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

This change is intended to be a test case for our vendor extension policy.  I believe this to be a case we clearly should accept, but it gives us an opportunity to discuss and set precedent on various policy and naming questions.  (I will comment on the review to highlight questions I think are worth discussion.)

I intent to bring this up at the next RISCV sync call, and ensure we have consensus.  Once this lands, I plan to use this extension to prototype selection lowering to conditional moves.  There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137350

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/XVentanaCondOps-valid.s

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