[clang] 7d7940f - [RISCV] add svinval extension
Piyou Chen via cfe-commits
cfe-commits at lists.llvm.org
Wed Oct 26 09:49:03 PDT 2022
Author: Piyou Chen
Date: 2022-10-26T09:45:30-07:00
New Revision: 7d7940fd7761e21b68f915e948389b87835d1304
URL: https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304
DIFF: https://github.com/llvm/llvm-project/commit/7d7940fd7761e21b68f915e948389b87835d1304.diff
LOG: [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction
Note: the svinval instructions defined in https://reviews.llvm.org/D117654
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136571
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/priv-valid.s
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 725d722bfc952..2d4aed24002e0 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -40,6 +40,7 @@
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
// CHECK-NOT: __riscv_svnapot
+// CHECK-NOT: __riscv_svinval
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -425,3 +426,9 @@
// RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
// CHECK-SVNAPOT-EXT: __riscv_svnapot 1000000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32isvinval -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s
+// CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index f5234ec0fcb30..387f2c29d26dc 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -52,6 +52,7 @@ on support follow.
``D`` Supported
``F`` Supported
``M`` Supported
+ ``Svinval`` Assembly Support
``V`` Supported
``Zba`` Supported
``Zbb`` Supported
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index ff5f1d7475189..1a899616ade94 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -103,6 +103,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zicbop", RISCVExtensionVersion{1, 0}},
{"svnapot", RISCVExtensionVersion{1, 0}},
+ {"svinval", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index a5c9f97d68a34..3813769a73dc7 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -392,6 +392,13 @@ def FeatureStdExtSvnapot
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
"'Svnapot' (NAPOT Translation Contiguity)">;
+def FeatureStdExtSvinval
+ : SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
+def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
+ AssemblerPredicate<(all_of FeatureStdExtSvinval),
+ "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
+
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index fb3bcf429d9a0..12bd105053e7a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -796,6 +796,7 @@ def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
let rs2 = 0b00101;
}
+let Predicates = [HasStdExtSvinval] in {
def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> {
let rd = 0;
let rs1 = 0;
@@ -807,13 +808,14 @@ def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
let rs1 = 0;
let rs2 = 0b00001;
}
+def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
+def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
+def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
+} // Predicates = [HasStdExtSvinval]
def SFENCE_VMA : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;
-def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
def HFENCE_VVMA : Priv_rr<"hfence.vvma", 0b0010001>, Sched<[]>;
def HFENCE_GVMA : Priv_rr<"hfence.gvma", 0b0110001>, Sched<[]>;
-def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
-def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
def HLV_B : HLoad_r<0b0110000, 0b00000, "hlv.b">, Sched<[]>;
def HLV_BU : HLoad_r<0b0110000, 0b00001, "hlv.bu">, Sched<[]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index f0980ea08e081..456dc00999aba 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,6 +86,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
bool HasStdExtSvnapot = false;
+ bool HasStdExtSvinval = false;
bool HasStdExtZmmul = false;
bool HasStdExtZawrs = false;
bool HasStdExtZtso = false;
@@ -184,6 +185,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
+ bool hasStdExtSvinval() const { return HasStdExtSvinval; }
bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
bool hasStdExtZtso() const { return HasStdExtZtso; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 45dd8679292d5..e0964e6ebbbfa 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -37,6 +37,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
+; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -74,6 +75,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
+; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV64SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
@@ -114,6 +116,7 @@
; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
+; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -153,6 +156,7 @@
; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
+; RV64SVINVAL: .attribute 5, "rv64i2p0_svinval1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
index e611e3c685847..a40950810aede 100644
--- a/llvm/test/MC/RISCV/priv-valid.s
+++ b/llvm/test/MC/RISCV/priv-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
+# RUN: | llvm-objdump --mattr=+svinval -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# CHECK-INST: uret
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