[PATCH] D136311: [CUDA,NVPTX] Implement __bf16 support for NVPTX.

[Artem Belevich via Phabricator via cfe-commits]

tra added inline comments.


================
Comment at: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td:186
+     !eq(name, "v2f16"): Float16x2Regs,
+     !eq(name, "bf16"): Float16Regs,
+     !eq(name, "v2bf16"): Float16x2Regs,
----------------
tra wrote:
> Allen wrote:
> > sorry for a basic question: what's the different between bf16 and f16 ?
> https://en.wikipedia.org/wiki/Bfloat16_floating-point_format
> 
If your question is why both bf16 and f16 use Float16Regs, then the answer is that both use 'untyped' 16-bit *integer * registers.
The difference from Int16Regs is that those are signed. PTX has some awkward restrictions on matching instructions and register kinds, even though under the hood it all boils down to everything using 32-bit registers.


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  https://reviews.llvm.org/D136311/new/

https://reviews.llvm.org/D136311