[clang] f8b8426 - [RISCV] Add Svnapot extension
Piyou Chen via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 24 01:33:28 PDT 2022
Author: Piyou Chen
Date: 2022-10-24T01:27:04-07:00
New Revision: f8b8426861a7a26ff60fe085800cc338591bee41
URL: https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41
DIFF: https://github.com/llvm/llvm-project/commit/f8b8426861a7a26ff60fe085800cc338591bee41.diff
LOG: [RISCV] Add Svnapot extension
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D136570
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index c1c29da5e18b0..725d722bfc952 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -39,6 +39,7 @@
// CHECK-NOT: __riscv_zk
// CHECK-NOT: __riscv_zicbom
// CHECK-NOT: __riscv_zicboz
+// CHECK-NOT: __riscv_svnapot
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -418,3 +419,9 @@
// RUN: -march=rv64iztso0p1 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
// CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32isvnapot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
+// RUN: %clang -target riscv64 -march=rv64isvnapot -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SVNAPOT-EXT %s
+// CHECK-SVNAPOT-EXT: __riscv_svnapot 1000000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 9cf7e04713655..ff5f1d7475189 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -101,6 +101,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zicbom", RISCVExtensionVersion{1, 0}},
{"zicboz", RISCVExtensionVersion{1, 0}},
{"zicbop", RISCVExtensionVersion{1, 0}},
+
+ {"svnapot", RISCVExtensionVersion{1, 0}},
};
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 822b2c44c2309..a5c9f97d68a34 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -388,6 +388,10 @@ def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
+def FeatureStdExtSvnapot
+ : SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
+ "'Svnapot' (NAPOT Translation Contiguity)">;
+
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 89fb7cb212a87..f0980ea08e081 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -85,6 +85,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZicbom = false;
bool HasStdExtZicboz = false;
bool HasStdExtZicbop = false;
+ bool HasStdExtSvnapot = false;
bool HasStdExtZmmul = false;
bool HasStdExtZawrs = false;
bool HasStdExtZtso = false;
@@ -182,6 +183,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZicbom() const { return HasStdExtZicbom; }
bool hasStdExtZicboz() const { return HasStdExtZicboz; }
bool hasStdExtZicbop() const { return HasStdExtZicbop; }
+ bool hasStdExtSvnapot() const { return HasStdExtSvnapot; }
bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool hasStdExtZmmul() const { return HasStdExtZmmul; }
bool hasStdExtZtso() const { return HasStdExtZtso; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 4136c6f37a16e..45dd8679292d5 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV32ZICBOM %s
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV32SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefix=RV64MZMMUL %s
@@ -72,6 +73,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefix=RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefix=RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefix=RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefix=RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
@@ -111,6 +113,7 @@
; RV32ZICBOM: .attribute 5, "rv32i2p0_zicbom1p0"
; RV32ZICBOZ: .attribute 5, "rv32i2p0_zicboz1p0"
; RV32ZICBOP: .attribute 5, "rv32i2p0_zicbop1p0"
+; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -149,6 +152,7 @@
; RV64ZICBOZ: .attribute 5, "rv64i2p0_zicboz1p0"
; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p0_zicbop1p0"
+; RV64SVNAPOT: .attribute 5, "rv64i2p0_svnapot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
define i32 @addi(i32 %a) {
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