[PATCH] D136040: [X86][1/2] Support PREFETCHI instructions

[Phoebe Wang via Phabricator via cfe-commits]

pengfei added inline comments.


================
Comment at: clang/lib/Headers/prfchiintrin.h:16
+/// Loads an instruction sequence containing the specified memory address into
+///    all level cache.
+///
----------------
craig.topper wrote:
> craig.topper wrote:
> > It looks old that this indented differently than the "Loads" on the line above.
> That should have said "It looks ODD that this indented differently..."
We use this indention in most existing headers. I guess it's intended to align with parameters' description. We follow this rule in the ISAs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136040/new/

https://reviews.llvm.org/D136040