[PATCH] D135951: [X86] SUPPORT RAO-INT

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86.td:259
+                                     "Support RAO-INT instructions",
+                                     [FeatureSSE2]>;
 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
----------------
Why do these require SSE2?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.h:801
+    RXOR,
+    RAND,
+
----------------
RKSimon wrote:
> very pedantic, but are these likely to get confused with ROR / RAND instructions? Would it be better to use a RAO_ prefix?
Why not AADD etc to match the instruction names?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135951/new/

https://reviews.llvm.org/D135951