[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

Fri Oct 14 09:38:04 PDT 2022

craig.topper added a comment.

In D116735#3857705 <https://reviews.llvm.org/D116735#3857705>, @zixuan-wu wrote:

> In D116735#3429850 <https://reviews.llvm.org/D116735#3429850>, @craig.topper wrote:
>
>> I'm seeing a regression on 401.bzip2 and possibly 471.astar. And I'm not seeing large improvements on 471.omnetpp or 483.xalancbmk.
>
> LGTM. But do you still get regression on spec? Or any improvements?

I only have numbers from my downstream repo which has a bunch of other changes. For one of our CPUs, I'm now seeing improvements, and another looks neutral. So I think we should move forward this. If there are individual regressions we can work on fixing those by improving the backend or fixing cost models or whatever.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735