[PATCH] D134745: [LV][Metadata] Add loop.interleave.enable for loop vectorizer

[Florian Hahn via Phabricator via cfe-commits]

fhahn added a comment.

> Adding this metadata allows {loop.vectorize.enable, false} to be used without disabling the whole pass.

Could you please describe the behavior in more detail here? The new metadata should also be documented in `LangRef`, the new pragma in https://clang.llvm.org/docs/LanguageExtensions.htm.

Will this change the existing behavior if only `llvm.loop.vectorize.enable == false`? To preserve backwards compatibility, I think the behavior shouldn;t change unless `llvm.loop.interleave.enable` is provided.

Also, shouldn't `#pragma clang loop vectorize(disable) interleave(enable)` be equivalent to `#pragma clang loop vectorize(enable) vectorize_width(1)`?



================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:2142
 
-  if (Hints.getInterleave() > 1) {
+  if (Hints.getInterleaveForce()) {
     // TODO: Interleave support is future work.
----------------
Will `getInterleaveForce()` return `ENABLED` if an interleave count > 1 is set through metadata?


================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:3013
   assert(!(SCEVCheckBlock->getParent()->hasOptSize() ||
-           (OptForSizeBasedOnProfile &&
-            Cost->Hints->getForce() != LoopVectorizeHints::FK_Enabled)) &&
+           (OptForSizeBasedOnProfile && Cost->Hints->getVectorizationForce() !=
+                                            LoopVectorizeHints::FK_Enabled)) &&
----------------
Should this check interleaving or vectorization forced?


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D134745