[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension
Xinlong Wu via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Mon Sep 12 18:35:33 PDT 2022
VincentWu updated this revision to Diff 459620.
VincentWu added a comment.
add newline at end of file
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D132819/new/
https://reviews.llvm.org/D132819
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zcb-invalid.s
llvm/test/MC/RISCV/rv32zcb-valid.s
llvm/test/MC/RISCV/rv32zcmp-Invalid.s
llvm/test/MC/RISCV/rv32zcmp-valid.s
llvm/test/MC/RISCV/rv64zcb-invalid.s
llvm/test/MC/RISCV/rv64zcb-valid.s
llvm/test/MC/RISCV/rv64zcmp-Invalid.s
llvm/test/MC/RISCV/rv64zcmp-valid.s
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