[PATCH] D133634: [clang] Allow vector of BitInt
Xiang Li via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Sun Sep 11 18:28:32 PDT 2022
python3kgae added a comment.
In D133634#3782999 <https://reviews.llvm.org/D133634#3782999>, @xbolva00 wrote:
> Missing IR tests. No issues in codegen?
>
> Very poor description. Why it was disabled? Why we can enable it now?
I'm not sure why it is disabled.
I guess it is never enabled and just assert in ASTContext::getExtVectorType before.
Then https://github.com/llvm/llvm-project/commit/c9edf843fcf954132271214445857498fb47bb72 make it an error instead of assert.
I'm enabling it for HLSL to use _BitInt(16) as 16bit int at https://reviews.llvm.org/D133668
This PR only makes sure it does not fail at AST level.
https://reviews.llvm.org/D133668 will fix the fail in Mangling when codeGen.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D133634/new/
https://reviews.llvm.org/D133634
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