[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

Mon Sep 5 08:21:00 PDT 2022

kito-cheng added a subscriber: khchen.
kito-cheng added a comment.

This is dump from my mailbox, few month ago I written a offlist mail to describe about RISC-V LTO status:

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LTO for RISC-V is really kind of a long long story. @khchen has been fighting for that for a long time, but he is no longer focusing on RISC-V.

A short summary is we still have issues with dealing with ABI, target features, and datalayout,

Datalayout is determined by target triple in most other targets, but RISC-V can't only use target triple to determine the datalayout.

So we need to keep ABI in somewhere and read that at LTO phase, the most ideal place is the module flags. We already did that[6], but that comes with a problem is it's too late to update datalayout when we start to read a module, because LLVM will use datalayout to infer some info like the alignment of loads[7], and that means we might re-read the whole LLVM IR again to get the IR with the right info, and that requires fixing multiple places in LLVM (see[2]. Still, I am not sure it's enough or not).

There is also an issue with how to store and determine the final LTO target features. For example, A object built with -march=rv64g and B object built with -march=rv64gc, so which arch should we use in the LTO code generation stage? see [5] for more discussion around this issue.

Currently, our downstream work-around is passing `-march` and `-mabi` into LTO by `-Wl,-plugin-opt=`, and ABI and ISA are determined by the linking stage to avoid (or work-around) the above issues.

Related open revision:
[1] https://reviews.llvm.org/D71387
[2] https://reviews.llvm.org/D72624 (This one is abandoned, but it
still necessary if we need store ABI info in module flags)
[3] https://reviews.llvm.org/D72245
[4] https://reviews.llvm.org/D102582
[5] https://reviews.llvm.org/D106347
[6] https://reviews.llvm.org/D72755

Other revision for ref.
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[7] https://reviews.llvm.org/D78403

Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D132843