[PATCH] D123450: [clang-format] Parse Verilog if statements

[Owen Pan via Phabricator via cfe-commits]

owenpan added inline comments.


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Comment at: clang/lib/Format/FormatToken.h:1550
+  bool isBlockBegin(const FormatToken &Tok, const FormatStyle &Style) const {
+    return Tok.is(TT_MacroBlockBegin) ||
+           (Style.isVerilog() ? isVerilogBegin(Tok) : Tok.is(tok::l_brace));
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Due of what `isBlockBegin()` is replacing in this patch, `TT_MacroBlockBegin` should be added in a separate patch (if it's correct to add it) along with corresponding unit tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123450/new/

https://reviews.llvm.org/D123450