[clang] 07e3476 - [X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit

[Bing1 Yu via cfe-commits]

Author: Bing1 Yu
Date: 2022-08-24T09:28:55+08:00
New Revision: 07e34763b02728857e1d6e8ccd2b82820eb3c0cc

URL: https://github.com/llvm/llvm-project/commit/07e34763b02728857e1d6e8ccd2b82820eb3c0cc
DIFF: https://github.com/llvm/llvm-project/commit/07e34763b02728857e1d6e8ccd2b82820eb3c0cc.diff

LOG: [X86] Emulate _rdrand64_step with two rdrand32 if it is 32bit

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D132141

Added: 
    

Modified: 
    clang/lib/Headers/immintrin.h
    clang/test/CodeGen/X86/rdrand-builtins.c

Removed: 
    


################################################################################
diff  --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index cca34783efaf4..9dfe3bfe6a6cd 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -287,6 +287,23 @@ _rdrand64_step(unsigned long long *__p)
 {
   return (int)__builtin_ia32_rdrand64_step(__p);
 }
+#else
+// We need to emulate the functionality of 64-bit rdrand with 2 32-bit
+// rdrand instructions.
+static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
+_rdrand64_step(unsigned long long *__p)
+{
+  unsigned int __lo, __hi;
+  int __res_lo = __builtin_ia32_rdrand32_step(&__lo);
+  int __res_hi = __builtin_ia32_rdrand32_step(&__hi);
+  if (__res_lo && __res_hi) {
+    *__p = ((unsigned long long)__hi << 32) | (unsigned long long)__lo;
+    return 1;
+  } else {
+    *__p = 0;
+    return 0;
+  }
+}
 #endif
 #endif /* __RDRND__ */
 

diff  --git a/clang/test/CodeGen/X86/rdrand-builtins.c b/clang/test/CodeGen/X86/rdrand-builtins.c
index 4eb17a400fa8b..b3ad463c55f24 100644
--- a/clang/test/CodeGen/X86/rdrand-builtins.c
+++ b/clang/test/CodeGen/X86/rdrand-builtins.c
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -no-opaque-pointers -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +rdrnd -target-feature +rdseed -emit-llvm -o - -Wall -Werror | FileCheck %s --check-prefixes=CHECK,X64
-// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding %s -triple=i386-unknown-unknown -target-feature +rdrnd -target-feature +rdseed -emit-llvm -o - -Wall -Werror | FileCheck %s --check-prefixes=CHECK
+// RUN: %clang_cc1 -no-opaque-pointers -ffreestanding %s -triple=i386-unknown-unknown -target-feature +rdrnd -target-feature +rdseed -emit-llvm -o - -Wall -Werror | FileCheck %s --check-prefixes=CHECK,X86
 
 #include <immintrin.h>
 
@@ -17,14 +17,61 @@ int rdrand32(unsigned *p) {
 // CHECK: store i32
 }
 
-#if __x86_64__
 int rdrand64(unsigned long long *p) {
   return _rdrand64_step(p);
 // X64: @rdrand64
 // X64: call { i64, i32 } @llvm.x86.rdrand.64
 // X64: store i64
+
+// X86-LABEL: @rdrand64(
+// X86-NEXT:  entry:
+// X86-NEXT:    [[RETVAL_I:%.*]] = alloca i32, align 4
+// X86-NEXT:    [[__P_ADDR_I:%.*]] = alloca i64*, align 4
+// X86-NEXT:    [[__LO_I:%.*]] = alloca i32, align 4
+// X86-NEXT:    [[__HI_I:%.*]] = alloca i32, align 4
+// X86-NEXT:    [[__RES_LO_I:%.*]] = alloca i32, align 4
+// X86-NEXT:    [[__RES_HI_I:%.*]] = alloca i32, align 4
+// X86-NEXT:    [[P_ADDR:%.*]] = alloca i64*, align 4
+// X86-NEXT:    store i64* [[P:%.*]], i64** [[P_ADDR]], align 4
+// X86-NEXT:    [[TMP0:%.*]] = load i64*, i64** [[P_ADDR]], align 4
+// X86-NEXT:    store i64* [[TMP0]], i64** [[__P_ADDR_I]], align 4
+// X86-NEXT:    [[TMP1:%.*]] = call { i32, i32 } @llvm.x86.rdrand.32()
+// X86-NEXT:    [[TMP2:%.*]] = extractvalue { i32, i32 } [[TMP1]], 0
+// X86-NEXT:    store i32 [[TMP2]], i32* [[__LO_I]], align 4
+// X86-NEXT:    [[TMP3:%.*]] = extractvalue { i32, i32 } [[TMP1]], 1
+// X86-NEXT:    store i32 [[TMP3]], i32* [[__RES_LO_I]], align 4
+// X86-NEXT:    [[TMP4:%.*]] = call { i32, i32 } @llvm.x86.rdrand.32()
+// X86-NEXT:    [[TMP5:%.*]] = extractvalue { i32, i32 } [[TMP4]], 0
+// X86-NEXT:    store i32 [[TMP5]], i32* [[__HI_I]], align 4
+// X86-NEXT:    [[TMP6:%.*]] = extractvalue { i32, i32 } [[TMP4]], 1
+// X86-NEXT:    store i32 [[TMP6]], i32* [[__RES_HI_I]], align 4
+// X86-NEXT:    [[TMP7:%.*]] = load i32, i32* [[__RES_LO_I]], align 4
+// X86-NEXT:    [[TOBOOL_I:%.*]] = icmp ne i32 [[TMP7]], 0
+// X86-NEXT:    br i1 [[TOBOOL_I]], label [[LAND_LHS_TRUE_I:%.*]], label [[IF_ELSE_I:%.*]]
+// X86:       land.lhs.true.i:
+// X86-NEXT:    [[TMP8:%.*]] = load i32, i32* [[__RES_HI_I]], align 4
+// X86-NEXT:    [[TOBOOL1_I:%.*]] = icmp ne i32 [[TMP8]], 0
+// X86-NEXT:    br i1 [[TOBOOL1_I]], label [[IF_THEN_I:%.*]], label [[IF_ELSE_I]]
+// X86:       if.then.i:
+// X86-NEXT:    [[TMP9:%.*]] = load i32, i32* [[__HI_I]], align 4
+// X86-NEXT:    [[CONV_I:%.*]] = zext i32 [[TMP9]] to i64
+// X86-NEXT:    [[SHL_I:%.*]] = shl i64 [[CONV_I]], 32
+// X86-NEXT:    [[TMP10:%.*]] = load i32, i32* [[__LO_I]], align 4
+// X86-NEXT:    [[CONV2_I:%.*]] = zext i32 [[TMP10]] to i64
+// X86-NEXT:    [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV2_I]]
+// X86-NEXT:    [[TMP11:%.*]] = load i64*, i64** [[__P_ADDR_I]], align 4
+// X86-NEXT:    store i64 [[OR_I]], i64* [[TMP11]], align 4
+// X86-NEXT:    store i32 1, i32* [[RETVAL_I]], align 4
+// X86-NEXT:    br label [[_RDRAND64_STEP_EXIT:%.*]]
+// X86:       if.else.i:
+// X86-NEXT:    [[TMP12:%.*]] = load i64*, i64** [[__P_ADDR_I]], align 4
+// X86-NEXT:    store i64 0, i64* [[TMP12]], align 4
+// X86-NEXT:    store i32 0, i32* [[RETVAL_I]], align 4
+// X86-NEXT:    br label [[_RDRAND64_STEP_EXIT]]
+// X86:       _rdrand64_step.exit:
+// X86-NEXT:    [[TMP13:%.*]] = load i32, i32* [[RETVAL_I]], align 4
+// X86-NEXT:    ret i32 [[TMP13]]
 }
-#endif
 
 int rdseed16(unsigned short *p) {
   return _rdseed16_step(p);