[clang] 1a60e00 - [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Fri Aug 19 09:11:35 PDT 2022
Author: Craig Topper
Date: 2022-08-19T09:11:22-07:00
New Revision: 1a60e003df8a8c03aae123bdec77e6a9db690862
URL: https://github.com/llvm/llvm-project/commit/1a60e003df8a8c03aae123bdec77e6a9db690862
DIFF: https://github.com/llvm/llvm-project/commit/1a60e003df8a8c03aae123bdec77e6a9db690862.diff
LOG: [RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D132197
Added:
Modified:
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/lib/Driver/ToolChains/BareMetal.cpp
Removed:
################################################################################
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 639285540c0a6..9b97e890c3523 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -968,14 +968,9 @@ void CodeGenModule::EmitOpenCLMetadata() {
void CodeGenModule::EmitBackendOptionsMetadata(
const CodeGenOptions CodeGenOpts) {
- switch (getTriple().getArch()) {
- default:
- break;
- case llvm::Triple::riscv32:
- case llvm::Triple::riscv64:
+ if (getTriple().isRISCV()) {
getModule().addModuleFlag(llvm::Module::Error, "SmallDataLimit",
CodeGenOpts.SmallDataLimit);
- break;
}
}
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index de6e045a9447f..c845e69c14e84 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -52,7 +52,7 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const llvm::Triple &Triple,
const llvm::opt::ArgList &Args,
const llvm::opt::Arg *A, StringRef Mcpu,
std::vector<StringRef> &Features) {
- bool Is64Bit = (Triple.getArch() == llvm::Triple::riscv64);
+ bool Is64Bit = Triple.isRISCV64();
llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
if (!llvm::RISCV::checkCPUKind(CPUKind, Is64Bit) ||
!llvm::RISCV::getCPUFeaturesExceptStdExt(CPUKind, Features)) {
@@ -163,9 +163,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
}
StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
- assert((Triple.getArch() == llvm::Triple::riscv32 ||
- Triple.getArch() == llvm::Triple::riscv64) &&
- "Unexpected triple");
+ assert(Triple.isRISCV() && "Unexpected triple");
// GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
// configured using `--with-abi=`, then the logic for the default choice is
@@ -213,7 +211,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
// We deviate from GCC's defaults here:
// - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
// - On all other OSs we use the double floating point calling convention.
- if (Triple.getArch() == llvm::Triple::riscv32) {
+ if (Triple.isRISCV32()) {
if (Triple.getOS() == llvm::Triple::UnknownOS)
return "ilp32";
else
@@ -228,9 +226,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
const llvm::Triple &Triple) {
- assert((Triple.getArch() == llvm::Triple::riscv32 ||
- Triple.getArch() == llvm::Triple::riscv64) &&
- "Unexpected triple");
+ assert(Triple.isRISCV() && "Unexpected triple");
// GCC's logic around choosing a default `-march=` is complex. If GCC is not
// configured using `--with-arch=`, then the logic for the default choice is
@@ -291,7 +287,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
// We deviate from GCC's defaults here:
// - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
- if (Triple.getArch() == llvm::Triple::riscv32) {
+ if (Triple.isRISCV32()) {
if (Triple.getOS() == llvm::Triple::UnknownOS)
return "rv32imac";
else
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 75b06d5e7d0d5..7b4b5a35205f0 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -39,7 +39,7 @@ static bool findRISCVMultilibs(const Driver &D,
StringRef Arch = riscv::getRISCVArch(Args, TargetTriple);
StringRef Abi = tools::riscv::getRISCVABI(Args, TargetTriple);
- if (TargetTriple.getArch() == llvm::Triple::riscv64) {
+ if (TargetTriple.isRISCV64()) {
Multilib Imac = makeMultilib("").flag("+march=rv64imac").flag("+mabi=lp64");
Multilib Imafdc = makeMultilib("/rv64imafdc/lp64d")
.flag("+march=rv64imafdc")
@@ -57,7 +57,7 @@ static bool findRISCVMultilibs(const Driver &D,
Result.Multilibs = MultilibSet().Either(Imac, Imafdc);
return Result.Multilibs.select(Flags, Result.SelectedMultilib);
}
- if (TargetTriple.getArch() == llvm::Triple::riscv32) {
+ if (TargetTriple.isRISCV32()) {
Multilib Imac =
makeMultilib("").flag("+march=rv32imac").flag("+mabi=ilp32");
Multilib I =
@@ -140,8 +140,7 @@ static bool isAArch64BareMetal(const llvm::Triple &Triple) {
}
static bool isRISCVBareMetal(const llvm::Triple &Triple) {
- if (Triple.getArch() != llvm::Triple::riscv32 &&
- Triple.getArch() != llvm::Triple::riscv64)
+ if (!Triple.isRISCV())
return false;
if (Triple.getVendor() != llvm::Triple::UnknownVendor)
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