[clang] 71fd661 - [RISCV][Clang] Support RVV policy functions.
Zakk Chen via cfe-commits
cfe-commits at lists.llvm.org
Mon Aug 1 10:45:51 PDT 2022
Author: Zakk Chen
Date: 2022-08-01T17:32:08Z
New Revision: 71fd66161d54b5a7ed78a1a94a1cc382cce78060
URL: https://github.com/llvm/llvm-project/commit/71fd66161d54b5a7ed78a1a94a1cc382cce78060
DIFF: https://github.com/llvm/llvm-project/commit/71fd66161d54b5a7ed78a1a94a1cc382cce78060.diff
LOG: [RISCV][Clang] Support RVV policy functions.
1. Add policy functions support and tests for vadd, vmv, vfmv and all load
instructions except segment load. I didn't add all combination of policy
functions in test because it seem not to make sense.
2. Rename HasUnMaskedOverloaded to SupportOverloading.
3. vmv.s.x for ta policy could not have overloaded API.
4. This patch does not support all operations, I will have other follow-up
patches support all.
[RFC] https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/137
Reviewed By: kito-cheng, fakepaper56, fakepaper56
Differential Revision: https://reviews.llvm.org/D126742
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/lib/Support/RISCVVIntrinsicUtils.cpp
clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 6b21f48110de7..2cfb185171e69 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -131,12 +131,12 @@
// There are a number of attributes that are used to constraint the number and
// shape of the builtins generated. Refer to the comments below for them.
-class Policy<int val>{
+class PolicyScheme<int val>{
int Value = val;
}
-def NonePolicy : Policy<0>;
-def HasPassthruOperand : Policy<1>;
-def HasPolicyOperand : Policy<2>;
+def NonePolicy : PolicyScheme<0>;
+def HasPassthruOperand : PolicyScheme<1>;
+def HasPolicyOperand : PolicyScheme<2>;
class RVVBuiltin<string suffix, string prototype, string type_range,
string overloaded_suffix = ""> {
@@ -186,7 +186,7 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// HasPolicyOperand: Has a policy operand. 0 is tail and mask undisturbed, 1 is
// tail agnostic, 2 is mask undisturbed, and 3 is tail and mask agnostic. The
// policy operand is located at the last position.
- Policy MaskedPolicyScheme = HasPolicyOperand;
+ PolicyScheme MaskedPolicyScheme = HasPolicyOperand;
// The policy scheme for unmasked intrinsic IR.
// It could be NonePolicy, HasPassthruOperand or HasPolicyOperand.
@@ -194,11 +194,21 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// undef, tail policy is tail agnostic, otherwise policy is tail undisturbed.
// HasPolicyOperand: Has a policy operand. 1 is tail agnostic and 0 is tail
// undisturbed.
- Policy UnMaskedPolicyScheme = NonePolicy;
+ PolicyScheme UnMaskedPolicyScheme = NonePolicy;
- // This builtin supports non-masked function overloading api.
- // All masked operations support overloading api.
- bit HasUnMaskedOverloaded = true;
+ // This builtin support tail agnostic and undisturbed policy.
+ bit HasTailPolicy = true;
+ // This builtin support mask agnostic and undisturbed policy.
+ bit HasMaskPolicy = true;
+
+ // This builtin prototype is tail undisturbed policy. It also means the
+ // default polcy without suffix is tail undisturbed.
+ bit IsPrototypeDefaultTU = false;
+
+ // This builtin prototype with TA or TAMA policy could not support overloading
+ // API. Other policy intrinsic functions would support overloading API with
+ // suffix `_tu`, `tumu`, `tuma`, `tamu` and `tama`.
+ bit SupportOverloading = true;
// This builtin is valid for the given Log2LMULs.
list<int> Log2LMUL = [0, 1, 2, 3, -1, -2, -3];
@@ -435,7 +445,7 @@ class RVVMaskUnaryBuiltin : RVVOutBuiltin<"m", "mm", "c"> {
class RVVMaskNullaryBuiltin : RVVOutBuiltin<"m", "m", "c"> {
let Name = NAME # "_m";
let HasMasked = false;
- let HasUnMaskedOverloaded = false;
+ let SupportOverloading = false;
}
class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
@@ -444,7 +454,8 @@ class RVVMaskOp0Builtin<string prototype> : RVVOp0Builtin<"m", prototype, "c"> {
}
let UnMaskedPolicyScheme = HasPolicyOperand,
- HasMaskedOffOperand = false in {
+ HasMaskedOffOperand = false,
+ IsPrototypeDefaultTU = true in {
multiclass RVVSlideBuiltinSet {
defm "" : RVVOutBuiltinSet<NAME, "csilxfd",
[["vx","v", "vvvz"]]>;
@@ -581,7 +592,7 @@ class IsFloat<string type> {
bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"));
}
-let HasUnMaskedOverloaded = false,
+let SupportOverloading = false,
MaskedPolicyScheme = NonePolicy in {
class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
let Name = "vlm_v";
@@ -590,7 +601,7 @@ let HasUnMaskedOverloaded = false,
}
}
-let HasUnMaskedOverloaded = false,
+let SupportOverloading = false,
UnMaskedPolicyScheme = HasPassthruOperand in {
multiclass RVVVLEBuiltin<list<string> types> {
let Name = NAME # "_v",
@@ -610,14 +621,16 @@ multiclass RVVVLEFFBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vleff",
MaskedIRName = "vleff_mask",
- HasUnMaskedOverloaded = false,
+ SupportOverloading = false,
+ UnMaskedPolicyScheme = HasPassthruOperand,
ManualCodegen = [{
{
- IntrinsicTypes = {ResultType, Ops[2]->getType()};
- Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
- Value *NewVL = Ops[1];
- Ops.erase(Ops.begin() + 1);
- Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ if (DefaultPolicy == TAIL_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ IntrinsicTypes = {ResultType, Ops[3]->getType()};
+ Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
+ Value *NewVL = Ops[2];
+ Ops.erase(Ops.begin() + 2);
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
@@ -633,7 +646,9 @@ multiclass RVVVLEFFBuiltin<list<string> types> {
{
// Move mask to right before vl.
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
+ if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
IntrinsicTypes = {ResultType, Ops[4]->getType()};
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
Value *NewVL = Ops[2];
@@ -642,8 +657,8 @@ multiclass RVVVLEFFBuiltin<list<string> types> {
llvm::Value *LoadValue = Builder.CreateCall(F, Ops, "");
llvm::Value *V = Builder.CreateExtractValue(LoadValue, {0});
// Store new_vl.
- clang::CharUnits Align =
- CGM.getNaturalPointeeTypeAlignment(E->getArg(3)->getType());
+ clang::CharUnits Align = CGM.getNaturalPointeeTypeAlignment(
+ E->getArg(E->getNumArgs()-2)->getType());
llvm::Value *Val = Builder.CreateExtractValue(LoadValue, {1});
Builder.CreateStore(Val, Address(NewVL, Val->getType(), Align));
return V;
@@ -663,7 +678,7 @@ multiclass RVVVLSEBuiltin<list<string> types> {
let Name = NAME # "_v",
IRName = "vlse",
MaskedIRName ="vlse_mask",
- HasUnMaskedOverloaded = false,
+ SupportOverloading = false,
UnMaskedPolicyScheme = HasPassthruOperand in {
foreach type = types in {
def : RVVOutBuiltin<"v", "vPCet", type>;
@@ -826,7 +841,7 @@ multiclass RVVUnitStridedSegLoad<string op> {
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
- HasUnMaskedOverloaded = false,
+ SupportOverloading = false,
ManualCodegen = [{
{
// builtin: (val0 address, val1 address, ..., ptr, vl)
@@ -901,7 +916,7 @@ multiclass RVVUnitStridedSegLoadFF<string op> {
IRName = op # nf # "ff",
MaskedIRName = op # nf # "ff_mask",
NF = nf,
- HasUnMaskedOverloaded = false,
+ SupportOverloading = false,
ManualCodegen = [{
{
// builtin: (val0 address, val1 address, ..., ptr, new_vl, vl)
@@ -980,7 +995,7 @@ multiclass RVVStridedSegLoad<string op> {
IRName = op # nf,
MaskedIRName = op # nf # "_mask",
NF = nf,
- HasUnMaskedOverloaded = false,
+ SupportOverloading = false,
ManualCodegen = [{
{
// builtin: (val0 address, val1 address, ..., ptr, stride, vl)
@@ -1357,20 +1372,22 @@ multiclass RVVPseudoVFUnaryBuiltin<string IR, string type_range> {
IntrinsicTypes = {ResultType,
Ops[0]->getType(), Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, Ops[0]);
- // insert undef passthru
- Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ if (DefaultPolicy == TAIL_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}],
MaskedManualCodegen = [{
{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
+ Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
// maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType,
Ops[1]->getType(),
Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, Ops[1]);
+ if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}] in {
@@ -1392,21 +1409,23 @@ multiclass RVVPseudoVWCVTBuiltin<string IR, string MName, string type_range,
cast<llvm::VectorType>(Ops[0]->getType())->getElementType(),
Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2]));
- // insert undef passthru
- Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ if (DefaultPolicy == TAIL_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}],
MaskedManualCodegen = [{
{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
+ Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
// maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType,
Ops[1]->getType(),
cast<llvm::VectorType>(Ops[1]->getType())->getElementType(),
Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2]));
+ if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}] in {
@@ -1430,21 +1449,23 @@ multiclass RVVPseudoVNCVTBuiltin<string IR, string MName, string type_range,
Ops[1]->getType(),
Ops[1]->getType()};
Ops.insert(Ops.begin() + 1, llvm::Constant::getNullValue(IntrinsicTypes[2]));
- // insert undef passthru
- Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
+ if (DefaultPolicy == TAIL_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}],
MaskedManualCodegen = [{
{
std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
- Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
+ Ops.push_back(ConstantInt::get(Ops.back()->getType(), DefaultPolicy));
// maskedoff, op1, mask, vl
IntrinsicTypes = {ResultType,
Ops[1]->getType(),
Ops[3]->getType(),
Ops[3]->getType()};
Ops.insert(Ops.begin() + 2, llvm::Constant::getNullValue(IntrinsicTypes[2]));
+ if (DefaultPolicy == TAIL_AGNOSTIC_MASK_AGNOSTIC)
+ Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
break;
}
}] in {
@@ -1615,6 +1636,9 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
// 7.8 Vector Load/Store Segment Instructions
+// TODO: Support policy function for segment load.
+let UnMaskedPolicyScheme = NonePolicy,
+ MaskedPolicyScheme = NonePolicy in {
defm : RVVUnitStridedSegLoad<"vlseg">;
defm : RVVUnitStridedSegLoadFF<"vlseg">;
defm : RVVStridedSegLoad<"vlsseg">;
@@ -1624,6 +1648,7 @@ defm : RVVUnitStridedSegStore<"vsseg">;
defm : RVVStridedSegStore<"vssseg">;
defm : RVVIndexedSegStore<"vsuxseg">;
defm : RVVIndexedSegStore<"vsoxseg">;
+}
// 12. Vector Integer Arithmetic Instructions
// 12.1. Vector Single-Width Integer Add and Subtract
@@ -1758,7 +1783,8 @@ defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi",
}
// 12.13. Vector Single-Width Integer Multiply-Add Instructions
-let UnMaskedPolicyScheme = HasPolicyOperand in {
+let UnMaskedPolicyScheme = HasPolicyOperand,
+ IsPrototypeDefaultTU = true in {
defm vmacc : RVVIntTerBuiltinSet;
defm vnmsac : RVVIntTerBuiltinSet;
defm vmadd : RVVIntTerBuiltinSet;
@@ -1800,14 +1826,13 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy,
// 12.16. Vector Integer Move Instructions
let HasMasked = false,
UnMaskedPolicyScheme = HasPassthruOperand,
- MaskedPolicyScheme = NonePolicy in {
- let OverloadedName = "vmv_v" in {
+ MaskedPolicyScheme = NonePolicy,
+ OverloadedName = "vmv_v" in {
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csil",
[["v", "Uv", "UvUv"]]>;
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilxfd",
[["v", "v", "vv"]]>;
- }
- let HasUnMaskedOverloaded = false in
+ let SupportOverloading = false in
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
[["x", "v", "ve"],
["x", "Uv", "UvUe"]]>;
@@ -1868,7 +1893,8 @@ let Log2LMUL = [-2, -1, 0, 1, 2] in {
}
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
-let UnMaskedPolicyScheme = HasPolicyOperand in {
+let UnMaskedPolicyScheme = HasPolicyOperand,
+ IsPrototypeDefaultTU = true in {
defm vfmacc : RVVFloatingTerBuiltinSet;
defm vfnmacc : RVVFloatingTerBuiltinSet;
defm vfmsac : RVVFloatingTerBuiltinSet;
@@ -1937,8 +1963,11 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy,
}
// 14.16. Vector Floating-Point Move Instruction
-let HasMasked = false, UnMaskedPolicyScheme = HasPassthruOperand,
- HasUnMaskedOverloaded = false, MaskedPolicyScheme = NonePolicy in
+let HasMasked = false,
+ UnMaskedPolicyScheme = HasPassthruOperand,
+ SupportOverloading = false,
+ MaskedPolicyScheme = NonePolicy,
+ OverloadedName = "vfmv_v" in
defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
[["f", "v", "ve"]]>;
@@ -1977,7 +2006,9 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
// 15. Vector Reduction Operations
// 15.1. Vector Single-Width Integer Reduction Instructions
-let MaskedPolicyScheme = NonePolicy in {
+let MaskedPolicyScheme = NonePolicy,
+ IsPrototypeDefaultTU = true,
+ HasMaskPolicy = false in {
defm vredsum : RVVIntReductionBuiltinSet;
defm vredmaxu : RVVUnsignedReductionBuiltin;
defm vredmax : RVVSignedReductionBuiltin;
@@ -2040,7 +2071,7 @@ def vmsif : RVVMaskUnaryBuiltin;
def vmsof : RVVMaskUnaryBuiltin;
}
-let UnMaskedPolicyScheme = HasPassthruOperand, HasUnMaskedOverloaded = false in {
+let UnMaskedPolicyScheme = HasPassthruOperand, SupportOverloading = false in {
// 16.8. Vector Iota Instruction
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
@@ -2056,7 +2087,9 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil",
[["s", "ve", "ev"],
["s", "UvUe", "UeUv"]]>;
- let OverloadedName = "vmv_s" in
+ let OverloadedName = "vmv_s", IsPrototypeDefaultTU = true,
+ UnMaskedPolicyScheme = HasPassthruOperand,
+ SupportOverloading = false in
defm vmv_s : RVVOutBuiltinSet<"vmv_s_x", "csil",
[["x", "v", "vve"],
["x", "Uv", "UvUvUe"]]>;
@@ -2067,7 +2100,9 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
let HasVL = false, OverloadedName = "vfmv_f" in
defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd",
[["s", "ve", "ev"]]>;
- let OverloadedName = "vfmv_s" in
+ let OverloadedName = "vfmv_s", IsPrototypeDefaultTU = true,
+ UnMaskedPolicyScheme = HasPassthruOperand,
+ SupportOverloading = false in
defm vfmv_s : RVVOutBuiltinSet<"vfmv_s_f", "xfd",
[["f", "v", "vve"],
["x", "Uv", "UvUvUe"]]>;
@@ -2143,7 +2178,7 @@ let HasMasked = false, HasVL = false, IRName = "" in {
}
}
- let Name = "vundefined", HasUnMaskedOverloaded = false,
+ let Name = "vundefined", SupportOverloading = false,
MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
return llvm::UndefValue::get(ResultType);
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 7ee4896eea095..756d8d13d6986 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -90,6 +90,21 @@ enum class TypeModifier : uint8_t {
LLVM_MARK_AS_BITMASK_ENUM(LMUL1),
};
+// The Lowerest two bit equal to policy value.
+enum Policy : uint8_t {
+ TU = 0, // For unmasked TU, last two bit is TUMU
+ TA = 1, // // For unmasked TA, last two bit is TAMU
+ TUMA = 2,
+ TAMA = 3,
+ TUMU = 4,
+ TAMU = 5,
+ MU = 6, // For masked MU, last two bit is TAMU
+ MA = 7, // For masked MA, last two bit is TAMA
+ TUM = 10, // For masked MA, last two bit is TUMA
+ TAM = 11, // For masked MA, last two bit is TAMA
+ PolicyNone,
+};
+
// PrototypeDescriptor is used to compute type info of arguments or return
// value.
struct PrototypeDescriptor {
@@ -290,9 +305,10 @@ class RVVIntrinsic {
std::string OverloadedName;
std::string IRName;
bool IsMasked;
+ bool HasMaskedOffOperand;
bool HasVL;
PolicyScheme Scheme;
- bool HasUnMaskedOverloaded;
+ bool SupportOverloading;
bool HasBuiltinAlias;
std::string ManualCodegen;
RVVTypePtr OutputType; // Builtin output type
@@ -301,17 +317,18 @@ class RVVIntrinsic {
// InputTypes. -1 means the return type.
std::vector<int64_t> IntrinsicTypes;
unsigned NF = 1;
+ Policy DefaultPolicy = Policy::PolicyNone;
public:
RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix,
llvm::StringRef OverloadedName, llvm::StringRef OverloadedSuffix,
llvm::StringRef IRName, bool IsMasked, bool HasMaskedOffOperand,
- bool HasVL, PolicyScheme Scheme, bool HasUnMaskedOverloaded,
+ bool HasVL, PolicyScheme Scheme, bool SupportOverloading,
bool HasBuiltinAlias, llvm::StringRef ManualCodegen,
const RVVTypes &Types,
const std::vector<int64_t> &IntrinsicTypes,
const std::vector<llvm::StringRef> &RequiredFeatures,
- unsigned NF);
+ unsigned NF, Policy DefaultPolicy, bool IsPrototypeDefaultTU);
~RVVIntrinsic() = default;
RVVTypePtr getOutputType() const { return OutputType; }
@@ -319,11 +336,16 @@ class RVVIntrinsic {
llvm::StringRef getBuiltinName() const { return BuiltinName; }
llvm::StringRef getName() const { return Name; }
llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
- bool hasPolicy() const { return Scheme != SchemeNone; }
- bool hasPassthruOperand() const { return Scheme == HasPassthruOperand; }
- bool hasPolicyOperand() const { return Scheme == HasPolicyOperand; }
- bool hasUnMaskedOverloaded() const { return HasUnMaskedOverloaded; }
+ bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
+ bool hasPassthruOperand() const {
+ return Scheme == PolicyScheme::HasPassthruOperand;
+ }
+ bool hasPolicyOperand() const {
+ return Scheme == PolicyScheme::HasPolicyOperand;
+ }
+ bool supportOverloading() const { return SupportOverloading; }
bool hasBuiltinAlias() const { return HasBuiltinAlias; }
bool hasManualCodegen() const { return !ManualCodegen.empty(); }
bool isMasked() const { return IsMasked; }
@@ -334,6 +356,14 @@ class RVVIntrinsic {
const std::vector<int64_t> &getIntrinsicTypes() const {
return IntrinsicTypes;
}
+ Policy getDefaultPolicy() const {
+ assert(DefaultPolicy != Policy::PolicyNone);
+ return DefaultPolicy;
+ }
+ unsigned getDefaultPolicyBits() const {
+ assert(DefaultPolicy != Policy::PolicyNone);
+ return static_cast<unsigned>(DefaultPolicy) & 3;
+ }
// Return the type string for a BUILTIN() macro in Builtins.def.
std::string getBuiltinTypeStr() const;
@@ -345,7 +375,17 @@ class RVVIntrinsic {
static llvm::SmallVector<PrototypeDescriptor>
computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
bool IsMasked, bool HasMaskedOffOperand, bool HasVL,
- unsigned NF);
+ unsigned NF, bool IsPrototypeDefaultTU,
+ PolicyScheme DefaultScheme,
+ Policy DefaultPolicy = Policy::PolicyNone);
+ static llvm::SmallVector<Policy>
+ getSupportedMaskedPolicies(bool HasTailPolicy, bool HasMaskPolicy);
+
+ static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy,
+ bool IsPrototypeDefaultTU, std::string &Name,
+ std::string &BuiltinName,
+ std::string &OverloadedName,
+ Policy &DefaultPolicy);
};
// RVVRequire should be sync'ed with target features, but only
@@ -401,6 +441,11 @@ struct RVVIntrinsicRecord {
bool HasMasked : 1;
bool HasVL : 1;
bool HasMaskedOffOperand : 1;
+ bool IsPrototypeDefaultTU : 1;
+ bool HasTailPolicy : 1;
+ bool HasMaskPolicy : 1;
+ uint8_t UnMaskedPolicyScheme : 2;
+ uint8_t MaskedPolicyScheme : 2;
};
llvm::raw_ostream &operator<<(llvm::raw_ostream &OS,
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 48e6a34bd73de..f1c7c5156f3d3 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -19105,6 +19105,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
unsigned NF = 1;
constexpr unsigned TAIL_UNDISTURBED = 0;
+ constexpr unsigned TAIL_AGNOSTIC = 1;
+ constexpr unsigned TAIL_AGNOSTIC_MASK_AGNOSTIC = 3;
+ int DefaultPolicy = TAIL_UNDISTURBED;
// Required for overloaded intrinsics.
llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 63194b7b2e366..4ab393b89d1b9 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -146,7 +146,8 @@ class RISCVIntrinsicManagerImpl : public sema::RISCVIntrinsicManager {
// Create RVVIntrinsicDef.
void InitRVVIntrinsic(const RVVIntrinsicRecord &Record, StringRef SuffixStr,
StringRef OverloadedSuffixStr, bool IsMask,
- RVVTypes &Types);
+ RVVTypes &Types, bool HasPolicy, Policy DefaultPolicy,
+ bool IsPrototypeDefaultTU);
// Create FunctionDecl for a vector intrinsic.
void CreateRVVIntrinsicDecl(LookupResult &LR, IdentifierInfo *II,
@@ -185,15 +186,31 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
ArrayRef<PrototypeDescriptor> OverloadedSuffixProto = ProtoSeq2ArrayRef(
Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);
+ PolicyScheme UnMaskedPolicyScheme =
+ static_cast<PolicyScheme>(Record.UnMaskedPolicyScheme);
+ PolicyScheme MaskedPolicyScheme =
+ static_cast<PolicyScheme>(Record.MaskedPolicyScheme);
+
llvm::SmallVector<PrototypeDescriptor> ProtoSeq =
- RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, /*IsMasked=*/false,
- /*HasMaskedOffOperand=*/false,
- Record.HasVL, Record.NF);
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicProtoSeq, /*IsMasked=*/false,
+ /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
+ Record.IsPrototypeDefaultTU, UnMaskedPolicyScheme);
llvm::SmallVector<PrototypeDescriptor> ProtoMaskSeq =
- RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, /*IsMasked=*/true,
- Record.HasMaskedOffOperand,
- Record.HasVL, Record.NF);
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
+ Record.HasVL, Record.NF, Record.IsPrototypeDefaultTU,
+ MaskedPolicyScheme);
+
+ bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
+ bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
+ // If unmasked builtin supports policy, they should be TU or TA.
+ llvm::SmallVector<Policy> SupportedUnMaskedPolicies = {Policy::TU,
+ Policy::TA};
+ llvm::SmallVector<Policy> SupportedMaskedPolicies =
+ RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy,
+ Record.HasMaskPolicy);
for (unsigned int TypeRangeMaskShift = 0;
TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);
@@ -242,33 +259,63 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
BaseType, Log2LMUL, OverloadedSuffixProto);
// Create non-masked intrinsic.
- InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types);
-
- if (Record.HasMasked) {
- // Create masked intrinsic.
- Optional<RVVTypes> MaskTypes = RVVType::computeTypes(
- BaseType, Log2LMUL, Record.NF, ProtoMaskSeq);
-
- InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true,
- *MaskTypes);
+ InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types,
+ UnMaskedHasPolicy, Policy::PolicyNone,
+ Record.IsPrototypeDefaultTU);
+
+ // Create non-masked policy intrinsic.
+ if (Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) {
+ for (auto P : SupportedUnMaskedPolicies) {
+ llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicProtoSeq, /*IsMasked=*/false,
+ /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
+ Record.IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+ Optional<RVVTypes> PolicyTypes = RVVType::computeTypes(
+ BaseType, Log2LMUL, Record.NF, PolicyPrototype);
+ InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
+ /*IsMask=*/false, *PolicyTypes, UnMaskedHasPolicy,
+ P, Record.IsPrototypeDefaultTU);
+ }
}
- }
- }
+ if (!Record.HasMasked)
+ continue;
+ // Create masked intrinsic.
+ Optional<RVVTypes> MaskTypes =
+ RVVType::computeTypes(BaseType, Log2LMUL, Record.NF, ProtoMaskSeq);
+ InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true,
+ *MaskTypes, MaskedHasPolicy, Policy::PolicyNone,
+ Record.IsPrototypeDefaultTU);
+ if (Record.MaskedPolicyScheme == PolicyScheme::SchemeNone)
+ continue;
+ // Create masked policy intrinsic.
+ for (auto P : SupportedMaskedPolicies) {
+ llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
+ Record.HasVL, Record.NF, Record.IsPrototypeDefaultTU,
+ MaskedPolicyScheme, P);
+ Optional<RVVTypes> PolicyTypes = RVVType::computeTypes(
+ BaseType, Log2LMUL, Record.NF, PolicyPrototype);
+ InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
+ /*IsMask=*/true, *PolicyTypes, MaskedHasPolicy, P,
+ Record.IsPrototypeDefaultTU);
+ }
+ } // End for
diff erent LMUL
+ } // End for
diff erent TypeRange
}
}
// Compute name and signatures for intrinsic with practical types.
void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
const RVVIntrinsicRecord &Record, StringRef SuffixStr,
- StringRef OverloadedSuffixStr, bool IsMask, RVVTypes &Signature) {
+ StringRef OverloadedSuffixStr, bool IsMasked, RVVTypes &Signature,
+ bool HasPolicy, Policy DefaultPolicy, bool IsPrototypeDefaultTU) {
// Function name, e.g. vadd_vv_i32m1.
std::string Name = Record.Name;
if (!SuffixStr.empty())
Name += "_" + SuffixStr.str();
- if (IsMask)
- Name += "_m";
-
// Overloaded function name, e.g. vadd.
std::string OverloadedName;
if (!Record.OverloadedName)
@@ -280,8 +327,10 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
// clang built-in function name, e.g. __builtin_rvv_vadd.
std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
- if (IsMask)
- BuiltinName += "_m";
+
+ RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, IsPrototypeDefaultTU,
+ Name, BuiltinName, OverloadedName,
+ DefaultPolicy);
// Put into IntrinsicList.
size_t Index = IntrinsicList.size();
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 513e6376f5aec..6d025cd95238f 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -849,13 +849,15 @@ RVVIntrinsic::RVVIntrinsic(
StringRef NewName, StringRef Suffix, StringRef NewOverloadedName,
StringRef OverloadedSuffix, StringRef IRName, bool IsMasked,
bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
- bool HasUnMaskedOverloaded, bool HasBuiltinAlias, StringRef ManualCodegen,
+ bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
const RVVTypes &OutInTypes, const std::vector<int64_t> &NewIntrinsicTypes,
- const std::vector<StringRef> &RequiredFeatures, unsigned NF)
- : IRName(IRName), IsMasked(IsMasked), HasVL(HasVL), Scheme(Scheme),
- HasUnMaskedOverloaded(HasUnMaskedOverloaded),
- HasBuiltinAlias(HasBuiltinAlias), ManualCodegen(ManualCodegen.str()),
- NF(NF) {
+ const std::vector<StringRef> &RequiredFeatures, unsigned NF,
+ Policy NewDefaultPolicy, bool IsPrototypeDefaultTU)
+ : IRName(IRName), IsMasked(IsMasked),
+ HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
+ SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
+ ManualCodegen(ManualCodegen.str()), NF(NF),
+ DefaultPolicy(NewDefaultPolicy) {
// Init BuiltinName, Name and OverloadedName
BuiltinName = NewName.str();
@@ -868,10 +870,9 @@ RVVIntrinsic::RVVIntrinsic(
Name += "_" + Suffix.str();
if (!OverloadedSuffix.empty())
OverloadedName += "_" + OverloadedSuffix.str();
- if (IsMasked) {
- BuiltinName += "_m";
- Name += "_m";
- }
+
+ updateNamesAndPolicy(IsMasked, hasPolicy(), IsPrototypeDefaultTU, Name,
+ BuiltinName, OverloadedName, DefaultPolicy);
// Init OutputType and InputTypes
OutputType = OutInTypes[0];
@@ -880,8 +881,8 @@ RVVIntrinsic::RVVIntrinsic(
// IntrinsicTypes is unmasked TA version index. Need to update it
// if there is merge operand (It is always in first operand).
IntrinsicTypes = NewIntrinsicTypes;
- if ((IsMasked && HasMaskedOffOperand) ||
- (!IsMasked && hasPassthruOperand())) {
+ if ((IsMasked && hasMaskedOffOperand()) ||
+ (!IsMasked && hasPassthruOperand() && !IsPrototypeDefaultTU)) {
for (auto &I : IntrinsicTypes) {
if (I >= 0)
I += NF;
@@ -909,18 +910,40 @@ std::string RVVIntrinsic::getSuffixStr(
return join(SuffixStrs, "_");
}
-llvm::SmallVector<PrototypeDescriptor>
-RVVIntrinsic::computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
- bool IsMasked, bool HasMaskedOffOperand,
- bool HasVL, unsigned NF) {
+llvm::SmallVector<PrototypeDescriptor> RVVIntrinsic::computeBuiltinTypes(
+ llvm::ArrayRef<PrototypeDescriptor> Prototype, bool IsMasked,
+ bool HasMaskedOffOperand, bool HasVL, unsigned NF,
+ bool IsPrototypeDefaultTU, PolicyScheme DefaultScheme,
+ Policy DefaultPolicy) {
SmallVector<PrototypeDescriptor> NewPrototype(Prototype.begin(),
Prototype.end());
+ // Update DefaultPolicy if need (TA or TAMA) for compute builtin types.
+ switch (DefaultPolicy) {
+ case Policy::MA:
+ DefaultPolicy = Policy::TAMA;
+ break;
+ case Policy::TAM:
+ DefaultPolicy = Policy::TAMA;
+ break;
+ case Policy::PolicyNone:
+ // Masked with no policy would not be TAMA.
+ if (!IsMasked) {
+ if (IsPrototypeDefaultTU)
+ DefaultPolicy = Policy::TU;
+ else
+ DefaultPolicy = Policy::TA;
+ }
+ break;
+ default:
+ break;
+ }
if (IsMasked) {
- // If HasMaskedOffOperand, insert result type as first input operand.
+ // If HasMaskedOffOperand, insert result type as first input operand if
+ // need.
if (HasMaskedOffOperand) {
- if (NF == 1) {
+ if (NF == 1 && DefaultPolicy != Policy::TAMA) {
NewPrototype.insert(NewPrototype.begin() + 1, NewPrototype[0]);
- } else {
+ } else if (NF > 1) {
// Convert
// (void, op0 address, op1 address, ...)
// to
@@ -943,6 +966,13 @@ RVVIntrinsic::computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
// If IsMasked, insert PrototypeDescriptor:Mask as first input operand.
NewPrototype.insert(NewPrototype.begin() + 1, PrototypeDescriptor::Mask);
}
+ } else if (NF == 1) {
+ bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
+ if (DefaultPolicy == Policy::TU && HasPassthruOp && !IsPrototypeDefaultTU)
+ NewPrototype.insert(NewPrototype.begin(), NewPrototype[0]);
+ else if (DefaultPolicy == Policy::TA && HasPassthruOp &&
+ IsPrototypeDefaultTU)
+ NewPrototype.erase(NewPrototype.begin() + 1);
}
// If HasVL, append PrototypeDescriptor:VL to last operand
@@ -951,6 +981,86 @@ RVVIntrinsic::computeBuiltinTypes(llvm::ArrayRef<PrototypeDescriptor> Prototype,
return NewPrototype;
}
+llvm::SmallVector<Policy>
+RVVIntrinsic::getSupportedMaskedPolicies(bool HasTailPolicy,
+ bool HasMaskPolicy) {
+ if (HasTailPolicy && HasMaskPolicy)
+ return {Policy::TUMA, Policy::TAMA, Policy::TUMU, Policy::TAMU};
+ else if (HasTailPolicy)
+ return {Policy::TUM, Policy::TAM};
+ return {Policy::MA, Policy::MU};
+}
+
+void RVVIntrinsic::updateNamesAndPolicy(bool IsMasked, bool HasPolicy,
+ bool IsPrototypeDefaultTU,
+ std::string &Name,
+ std::string &BuiltinName,
+ std::string &OverloadedName,
+ Policy &DefaultPolicy) {
+
+ auto appendPolicySuffix = [&](const std::string &suffix) {
+ Name += suffix;
+ BuiltinName += suffix;
+ OverloadedName += suffix;
+ };
+
+ switch (DefaultPolicy) {
+ case Policy::TU:
+ appendPolicySuffix("_tu");
+ break;
+ case Policy::TA:
+ appendPolicySuffix("_ta");
+ break;
+ case Policy::MU:
+ appendPolicySuffix("_mu");
+ DefaultPolicy = Policy::TAMU;
+ break;
+ case Policy::MA:
+ appendPolicySuffix("_ma");
+ DefaultPolicy = Policy::TAMA;
+ break;
+ case Policy::TUM:
+ appendPolicySuffix("_tum");
+ DefaultPolicy = Policy::TUMA;
+ break;
+ case Policy::TAM:
+ appendPolicySuffix("_tam");
+ DefaultPolicy = Policy::TAMA;
+ break;
+ case Policy::TUMU:
+ appendPolicySuffix("_tumu");
+ break;
+ case Policy::TAMU:
+ appendPolicySuffix("_tamu");
+ break;
+ case Policy::TUMA:
+ appendPolicySuffix("_tuma");
+ break;
+ case Policy::TAMA:
+ appendPolicySuffix("_tama");
+ break;
+ default:
+ if (IsMasked) {
+ Name += "_m";
+ // FIXME: Currently _m default policy implementation is
diff erent with
+ // RVV intrinsic spec (TUMA)
+ DefaultPolicy = Policy::TUMU;
+ if (HasPolicy)
+ BuiltinName += "_tumu";
+ else
+ BuiltinName += "_m";
+ } else if (IsPrototypeDefaultTU) {
+ DefaultPolicy = Policy::TU;
+ if (HasPolicy)
+ BuiltinName += "_tu";
+ } else {
+ DefaultPolicy = Policy::TA;
+ if (HasPolicy)
+ BuiltinName += "_ta";
+ }
+ }
+}
+
SmallVector<PrototypeDescriptor> parsePrototypes(StringRef Prototypes) {
SmallVector<PrototypeDescriptor> PrototypeDescriptors;
const StringRef Primaries("evwqom0ztul");
@@ -993,6 +1103,11 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
OS << (int)Record.HasMasked << ",";
OS << (int)Record.HasVL << ",";
OS << (int)Record.HasMaskedOffOperand << ",";
+ OS << (int)Record.IsPrototypeDefaultTU << ",";
+ OS << (int)Record.HasTailPolicy << ",";
+ OS << (int)Record.HasMaskPolicy << ",";
+ OS << (int)Record.UnMaskedPolicyScheme << ",";
+ OS << (int)Record.MaskedPolicyScheme << ",";
OS << "},\n";
return OS;
}
diff --git a/clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c b/clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
index 19abf92e92fe4..b1615c9090bb0 100644
--- a/clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
+++ b/clang/test/CodeGen/RISCV/riscv-attr-builtin-alias.c
@@ -10,7 +10,7 @@
static inline __attribute__((__always_inline__, __nodebug__))
__rvv_generic
-__attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv)))
+__attribute__((clang_builtin_alias(__builtin_rvv_vadd_vv_ta)))
vint8m1_t vadd_generic (vint8m1_t op0, vint8m1_t op1, size_t op2);
// CHECK-LABEL: @test(
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
index ba85e0326a8d5..626b6233cbbdb 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
@@ -1588,3 +1588,219 @@ vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8
vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd(mask, maskedoff, op1, op2, vl);
}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tu(vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tu(vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tu(vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tu(vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_ta(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_ta(vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_ta(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_ta(vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tama(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tama(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tama(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tama(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_tamu(mask, merge, op1, op2, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
index 3702b7c7b63e0..1152cf09110d6 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
@@ -148,3 +148,21 @@ double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) { return vfmv_f(src); }
vfloat64m8_t test_vfmv_s_f_f64m8(vfloat64m8_t dst, double src, size_t vl) {
return vfmv_s(dst, src, vl);
}
+
+// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_v_f_f32mf2_tu(vfloat32mf2_t merge, float src, size_t vl) {
+ return vfmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfmv_s_f_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_s_f_f32mf2_tu(vfloat32mf2_t merge, float src, size_t vl) {
+ return vfmv_s_tu(merge, src, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
index ee4809d2ffece..1353cdc8cadf8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
@@ -594,3 +594,83 @@ vfloat16m4_t test_vle16_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _
vfloat16m8_t test_vle16_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t vl) {
return vle16(mask, maskedoff, base, vl);
}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tu(vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_tu(merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tu(vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_tu(merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_tuma(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_tuma(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_tumu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_tumu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_tamu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_tamu(mask, merge, base, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
index 5f3c47e84a139..9c81e7ae36b1f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
@@ -3826,3 +3826,182 @@ vfloat64m8_t test_vloxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, cons
return vloxei64(mask, maskedoff, base, bindex, vl);
}
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_ta(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_ta(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_ta(const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tama(vbool64_t mask, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tama(vbool64_t mask, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_tamu(mask, merge, base, bindex, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
index ac5f72c1ee7b7..54ec5b99e5bc8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
@@ -700,3 +700,123 @@ vfloat16m4_t test_vlse16_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const
vfloat16m8_t test_vlse16_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
return vlse16(mask, maskedoff, base, bstride, vl);
}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tamu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tamu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_tamu(mask, merge, base, bstride, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
index 9d0ec5e2c2931..e2d18bc82aedd 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
@@ -2255,6 +2255,7 @@ vint16m8_t test_vluxei16_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, const in
return vluxei16(mask, maskedoff, base, bindex, vl);
}
+//
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -3824,3 +3825,183 @@ vfloat64m4_t test_vluxei64_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, con
vfloat64m8_t test_vluxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) {
return vluxei64(mask, maskedoff, base, bindex, vl);
}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_ta(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_ta(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_ta(const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tama(vbool64_t mask, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tama(vbool64_t mask, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_tamu(mask, merge, base, bindex, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
index 466621c19db86..db307ddb6d85d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
@@ -1177,3 +1177,93 @@ uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) { return vmv_x(src); }
vuint64m8_t test_vmv_s_x_u64m8(vuint64m8_t dst, uint64_t src, size_t vl) {
return vmv_s(dst, src, vl);
}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_v_i32mf2_tu(vint32mf2_t merge, vint32mf2_t src, size_t vl) {
+ return vmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_x_i32mf2_tu(vint32mf2_t merge, int32_t src, size_t vl) {
+ return vmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_v_u32mf2_tu(vuint32mf2_t merge, vuint32mf2_t src, size_t vl) {
+ return vmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_x_u32mf2_tu(vuint32mf2_t merge, uint32_t src, size_t vl) {
+ return vmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_v_i32mf2_ta(vint32mf2_t src, size_t vl) {
+ return vmv_v_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_v_u32mf2_ta(vuint32mf2_t src, size_t vl) {
+ return vmv_v_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vmv_v_v_f32mf2_tu(vfloat32mf2_t merge, vfloat32mf2_t src, size_t vl) {
+ return vmv_v_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vmv_v_v_f32mf2_ta(vfloat32mf2_t src, size_t vl) {
+ return vmv_v_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_s_x_i32mf2_tu(vint32mf2_t merge, int32_t src, size_t vl) {
+ return vmv_s_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_s_x_u32mf2_tu(vuint32mf2_t merge, uint32_t src, size_t vl) {
+ return vmv_s_tu(merge, src, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
index 5efe2067c2510..2ecd7c43b5679 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
@@ -1588,3 +1588,219 @@ vuint64m8_t test_vadd_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8
vuint64m8_t test_vadd_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t op1, uint64_t op2, size_t vl) {
return vadd_vx_u64m8_m(mask, maskedoff, op1, op2, vl);
}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tu(vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tu(vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tu(vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tu(vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_tu(merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_ta(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_ta(vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_ta(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_ta(vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_ta(op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_tuma(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_tumu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tama(vbool64_t mask, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tama(vbool64_t mask, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tama(vbool64_t mask, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tama(vbool64_t mask, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_tama(mask, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vv_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return vadd_vv_i8mf8_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vint8mf8_t test_vadd_vx_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, vint8mf8_t op1, int8_t op2, size_t vl) {
+ return vadd_vx_i8mf8_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vv_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vv_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
+ return vadd_vv_u8mf8_tamu(mask, merge, op1, op2, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vadd_vx_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]]
+//
+vuint8mf8_t test_vadd_vx_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, vuint8mf8_t op1, uint8_t op2, size_t vl) {
+ return vadd_vx_u8mf8_tamu(mask, merge, op1, op2, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
index a59cc67d9aacb..9c47af4bc285f 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
@@ -410,3 +410,39 @@ _Float16 test_vfmv_f_s_f16m8_f16 (vfloat16m8_t src) {
vfloat16m8_t test_vfmv_s_f_f16m8 (vfloat16m8_t dest, _Float16 src, size_t vl) {
return vfmv_s_f_f16m8(dest, src, vl);
}
+
+// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_v_f_f32mf2_tu (vfloat32mf2_t merge, float src, size_t vl) {
+ return vfmv_v_f_f32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfmv_v_f_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.i64(<vscale x 1 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_v_f_f32mf2_ta (float src, size_t vl) {
+ return vfmv_v_f_f32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfmv_s_f_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_s_f_f32mf2_tu (vfloat32mf2_t merge, float src, size_t vl) {
+ return vfmv_s_f_f32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vfmv_s_f_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32.i64(<vscale x 1 x float> undef, float [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vfmv_s_f_f32mf2_ta (float src, size_t vl) {
+ return vfmv_s_f_f32mf2_ta(src, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
index dd68c215d785b..110a406f230b2 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
@@ -1254,3 +1254,123 @@ vbool32_t test_vlm_v_b32(const uint8_t *base, size_t vl) {
vbool64_t test_vlm_v_b64(const uint8_t *base, size_t vl) {
return vlm_v_b64(base, vl);
}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tu(vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_tu(merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tu(vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_tu(merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_ta(const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_ta(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_ta(const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_ta(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tuma(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_tuma(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tuma(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_tuma(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tumu(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_tumu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_tumu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tama(vbool64_t mask, const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_tama(mask, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> undef, <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tama(vbool64_t mask, const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_tama(mask, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_i8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vint8mf8_t test_vle8_v_i8mf8_tamu(vbool64_t mask, vint8mf8_t merge, const int8_t *base, size_t vl) {
+ return vle8_v_i8mf8_tamu(mask, merge, base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle8_v_u8mf8_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vle.mask.nxv1i8.i64(<vscale x 1 x i8> [[MERGE:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
+//
+vuint8mf8_t test_vle8_v_u8mf8_tamu(vbool64_t mask, vuint8mf8_t merge, const uint8_t *base, size_t vl) {
+ return vle8_v_u8mf8_tamu(mask, merge, base, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
index 35318ed317e0a..4fe6e5b646303 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
@@ -15,7 +15,7 @@
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
//
-vint8mf8_t test_vle8ff_v_i8mf8 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf8_t test_vle8ff_v_i8mf8(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf8(base, new_vl, vl);
}
@@ -28,7 +28,7 @@ vint8mf8_t test_vle8ff_v_i8mf8 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
//
-vint8mf4_t test_vle8ff_v_i8mf4 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf4_t test_vle8ff_v_i8mf4(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf4(base, new_vl, vl);
}
@@ -41,7 +41,7 @@ vint8mf4_t test_vle8ff_v_i8mf4 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
//
-vint8mf2_t test_vle8ff_v_i8mf2 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf2_t test_vle8ff_v_i8mf2(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf2(base, new_vl, vl);
}
@@ -54,7 +54,7 @@ vint8mf2_t test_vle8ff_v_i8mf2 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
//
-vint8m1_t test_vle8ff_v_i8m1 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m1_t test_vle8ff_v_i8m1(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m1(base, new_vl, vl);
}
@@ -67,7 +67,7 @@ vint8m1_t test_vle8ff_v_i8m1 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
//
-vint8m2_t test_vle8ff_v_i8m2 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m2_t test_vle8ff_v_i8m2(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m2(base, new_vl, vl);
}
@@ -80,7 +80,7 @@ vint8m2_t test_vle8ff_v_i8m2 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
//
-vint8m4_t test_vle8ff_v_i8m4 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m4_t test_vle8ff_v_i8m4(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m4(base, new_vl, vl);
}
@@ -93,7 +93,7 @@ vint8m4_t test_vle8ff_v_i8m4 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
//
-vint8m8_t test_vle8ff_v_i8m8 (const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m8_t test_vle8ff_v_i8m8(const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m8(base, new_vl, vl);
}
@@ -106,7 +106,7 @@ vint8m8_t test_vle8ff_v_i8m8 (const int8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
//
-vuint8mf8_t test_vle8ff_v_u8mf8 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf8_t test_vle8ff_v_u8mf8(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf8(base, new_vl, vl);
}
@@ -119,7 +119,7 @@ vuint8mf8_t test_vle8ff_v_u8mf8 (const uint8_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
//
-vuint8mf4_t test_vle8ff_v_u8mf4 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf4_t test_vle8ff_v_u8mf4(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf4(base, new_vl, vl);
}
@@ -132,7 +132,7 @@ vuint8mf4_t test_vle8ff_v_u8mf4 (const uint8_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
//
-vuint8mf2_t test_vle8ff_v_u8mf2 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf2_t test_vle8ff_v_u8mf2(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf2(base, new_vl, vl);
}
@@ -145,7 +145,7 @@ vuint8mf2_t test_vle8ff_v_u8mf2 (const uint8_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
//
-vuint8m1_t test_vle8ff_v_u8m1 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m1_t test_vle8ff_v_u8m1(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m1(base, new_vl, vl);
}
@@ -158,7 +158,7 @@ vuint8m1_t test_vle8ff_v_u8m1 (const uint8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
//
-vuint8m2_t test_vle8ff_v_u8m2 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m2_t test_vle8ff_v_u8m2(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m2(base, new_vl, vl);
}
@@ -171,7 +171,7 @@ vuint8m2_t test_vle8ff_v_u8m2 (const uint8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
//
-vuint8m4_t test_vle8ff_v_u8m4 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m4_t test_vle8ff_v_u8m4(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m4(base, new_vl, vl);
}
@@ -184,7 +184,7 @@ vuint8m4_t test_vle8ff_v_u8m4 (const uint8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
//
-vuint8m8_t test_vle8ff_v_u8m8 (const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m8_t test_vle8ff_v_u8m8(const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m8(base, new_vl, vl);
}
@@ -197,7 +197,7 @@ vuint8m8_t test_vle8ff_v_u8m8 (const uint8_t *base, size_t *new_vl, size_t vl) {
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
//
-vint8mf8_t test_vle8ff_v_i8mf8_m (vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf8_t test_vle8ff_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -210,7 +210,7 @@ vint8mf8_t test_vle8ff_v_i8mf8_m (vbool64_t mask, vint8mf8_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
//
-vint8mf4_t test_vle8ff_v_i8mf4_m (vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf4_t test_vle8ff_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -223,7 +223,7 @@ vint8mf4_t test_vle8ff_v_i8mf4_m (vbool32_t mask, vint8mf4_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
//
-vint8mf2_t test_vle8ff_v_i8mf2_m (vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8mf2_t test_vle8ff_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -236,7 +236,7 @@ vint8mf2_t test_vle8ff_v_i8mf2_m (vbool16_t mask, vint8mf2_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
//
-vint8m1_t test_vle8ff_v_i8m1_m (vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m1_t test_vle8ff_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -249,7 +249,7 @@ vint8m1_t test_vle8ff_v_i8m1_m (vbool8_t mask, vint8m1_t maskedoff, const int8_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
//
-vint8m2_t test_vle8ff_v_i8m2_m (vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m2_t test_vle8ff_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -262,7 +262,7 @@ vint8m2_t test_vle8ff_v_i8m2_m (vbool4_t mask, vint8m2_t maskedoff, const int8_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
//
-vint8m4_t test_vle8ff_v_i8m4_m (vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m4_t test_vle8ff_v_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -275,7 +275,7 @@ vint8m4_t test_vle8ff_v_i8m4_m (vbool2_t mask, vint8m4_t maskedoff, const int8_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
//
-vint8m8_t test_vle8ff_v_i8m8_m (vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
+vint8m8_t test_vle8ff_v_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_i8m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -288,7 +288,7 @@ vint8m8_t test_vle8ff_v_i8m8_m (vbool1_t mask, vint8m8_t maskedoff, const int8_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP2]]
//
-vuint8mf8_t test_vle8ff_v_u8mf8_m (vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf8_t test_vle8ff_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -301,7 +301,7 @@ vuint8mf8_t test_vle8ff_v_u8mf8_m (vbool64_t mask, vuint8mf8_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP2]]
//
-vuint8mf4_t test_vle8ff_v_u8mf4_m (vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf4_t test_vle8ff_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -314,7 +314,7 @@ vuint8mf4_t test_vle8ff_v_u8mf4_m (vbool32_t mask, vuint8mf4_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP2]]
//
-vuint8mf2_t test_vle8ff_v_u8mf2_m (vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8mf2_t test_vle8ff_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -327,7 +327,7 @@ vuint8mf2_t test_vle8ff_v_u8mf2_m (vbool16_t mask, vuint8mf2_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP2]]
//
-vuint8m1_t test_vle8ff_v_u8m1_m (vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m1_t test_vle8ff_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -340,7 +340,7 @@ vuint8m1_t test_vle8ff_v_u8m1_m (vbool8_t mask, vuint8m1_t maskedoff, const uint
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP2]]
//
-vuint8m2_t test_vle8ff_v_u8m2_m (vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m2_t test_vle8ff_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -353,7 +353,7 @@ vuint8m2_t test_vle8ff_v_u8m2_m (vbool4_t mask, vuint8m2_t maskedoff, const uint
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP2]]
//
-vuint8m4_t test_vle8ff_v_u8m4_m (vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m4_t test_vle8ff_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -366,7 +366,7 @@ vuint8m4_t test_vle8ff_v_u8m4_m (vbool2_t mask, vuint8m4_t maskedoff, const uint
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP2]]
//
-vuint8m8_t test_vle8ff_v_u8m8_m (vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
+vuint8m8_t test_vle8ff_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) {
return vle8ff_v_u8m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -379,7 +379,7 @@ vuint8m8_t test_vle8ff_v_u8m8_m (vbool1_t mask, vuint8m8_t maskedoff, const uint
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
//
-vint16mf4_t test_vle16ff_v_i16mf4 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16mf4_t test_vle16ff_v_i16mf4(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf4(base, new_vl, vl);
}
@@ -392,7 +392,7 @@ vint16mf4_t test_vle16ff_v_i16mf4 (const int16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
//
-vint16mf2_t test_vle16ff_v_i16mf2 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16mf2_t test_vle16ff_v_i16mf2(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf2(base, new_vl, vl);
}
@@ -405,7 +405,7 @@ vint16mf2_t test_vle16ff_v_i16mf2 (const int16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
//
-vint16m1_t test_vle16ff_v_i16m1 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m1_t test_vle16ff_v_i16m1(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m1(base, new_vl, vl);
}
@@ -418,7 +418,7 @@ vint16m1_t test_vle16ff_v_i16m1 (const int16_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
//
-vint16m2_t test_vle16ff_v_i16m2 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m2_t test_vle16ff_v_i16m2(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m2(base, new_vl, vl);
}
@@ -431,7 +431,7 @@ vint16m2_t test_vle16ff_v_i16m2 (const int16_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
//
-vint16m4_t test_vle16ff_v_i16m4 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m4_t test_vle16ff_v_i16m4(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m4(base, new_vl, vl);
}
@@ -444,7 +444,7 @@ vint16m4_t test_vle16ff_v_i16m4 (const int16_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
//
-vint16m8_t test_vle16ff_v_i16m8 (const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m8_t test_vle16ff_v_i16m8(const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m8(base, new_vl, vl);
}
@@ -457,7 +457,7 @@ vint16m8_t test_vle16ff_v_i16m8 (const int16_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
//
-vuint16mf4_t test_vle16ff_v_u16mf4 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16mf4_t test_vle16ff_v_u16mf4(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf4(base, new_vl, vl);
}
@@ -470,7 +470,7 @@ vuint16mf4_t test_vle16ff_v_u16mf4 (const uint16_t *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
//
-vuint16mf2_t test_vle16ff_v_u16mf2 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16mf2_t test_vle16ff_v_u16mf2(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf2(base, new_vl, vl);
}
@@ -483,7 +483,7 @@ vuint16mf2_t test_vle16ff_v_u16mf2 (const uint16_t *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
//
-vuint16m1_t test_vle16ff_v_u16m1 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m1_t test_vle16ff_v_u16m1(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m1(base, new_vl, vl);
}
@@ -496,7 +496,7 @@ vuint16m1_t test_vle16ff_v_u16m1 (const uint16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
//
-vuint16m2_t test_vle16ff_v_u16m2 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m2_t test_vle16ff_v_u16m2(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m2(base, new_vl, vl);
}
@@ -509,7 +509,7 @@ vuint16m2_t test_vle16ff_v_u16m2 (const uint16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
//
-vuint16m4_t test_vle16ff_v_u16m4 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m4_t test_vle16ff_v_u16m4(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m4(base, new_vl, vl);
}
@@ -522,7 +522,7 @@ vuint16m4_t test_vle16ff_v_u16m4 (const uint16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
//
-vuint16m8_t test_vle16ff_v_u16m8 (const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m8_t test_vle16ff_v_u16m8(const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m8(base, new_vl, vl);
}
@@ -535,7 +535,7 @@ vuint16m8_t test_vle16ff_v_u16m8 (const uint16_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
//
-vint16mf4_t test_vle16ff_v_i16mf4_m (vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16mf4_t test_vle16ff_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -548,7 +548,7 @@ vint16mf4_t test_vle16ff_v_i16mf4_m (vbool64_t mask, vint16mf4_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
//
-vint16mf2_t test_vle16ff_v_i16mf2_m (vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16mf2_t test_vle16ff_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -561,7 +561,7 @@ vint16mf2_t test_vle16ff_v_i16mf2_m (vbool32_t mask, vint16mf2_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
//
-vint16m1_t test_vle16ff_v_i16m1_m (vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m1_t test_vle16ff_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -574,7 +574,7 @@ vint16m1_t test_vle16ff_v_i16m1_m (vbool16_t mask, vint16m1_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
//
-vint16m2_t test_vle16ff_v_i16m2_m (vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m2_t test_vle16ff_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -587,7 +587,7 @@ vint16m2_t test_vle16ff_v_i16m2_m (vbool8_t mask, vint16m2_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
//
-vint16m4_t test_vle16ff_v_i16m4_m (vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m4_t test_vle16ff_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -600,7 +600,7 @@ vint16m4_t test_vle16ff_v_i16m4_m (vbool4_t mask, vint16m4_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
//
-vint16m8_t test_vle16ff_v_i16m8_m (vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
+vint16m8_t test_vle16ff_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_i16m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -613,7 +613,7 @@ vint16m8_t test_vle16ff_v_i16m8_m (vbool2_t mask, vint16m8_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP2]]
//
-vuint16mf4_t test_vle16ff_v_u16mf4_m (vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16mf4_t test_vle16ff_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -626,7 +626,7 @@ vuint16mf4_t test_vle16ff_v_u16mf4_m (vbool64_t mask, vuint16mf4_t maskedoff, co
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP2]]
//
-vuint16mf2_t test_vle16ff_v_u16mf2_m (vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16mf2_t test_vle16ff_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -639,7 +639,7 @@ vuint16mf2_t test_vle16ff_v_u16mf2_m (vbool32_t mask, vuint16mf2_t maskedoff, co
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP2]]
//
-vuint16m1_t test_vle16ff_v_u16m1_m (vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m1_t test_vle16ff_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -652,7 +652,7 @@ vuint16m1_t test_vle16ff_v_u16m1_m (vbool16_t mask, vuint16m1_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP2]]
//
-vuint16m2_t test_vle16ff_v_u16m2_m (vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m2_t test_vle16ff_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -665,7 +665,7 @@ vuint16m2_t test_vle16ff_v_u16m2_m (vbool8_t mask, vuint16m2_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP2]]
//
-vuint16m4_t test_vle16ff_v_u16m4_m (vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m4_t test_vle16ff_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -678,7 +678,7 @@ vuint16m4_t test_vle16ff_v_u16m4_m (vbool4_t mask, vuint16m4_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP2]]
//
-vuint16m8_t test_vle16ff_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
+vuint16m8_t test_vle16ff_v_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) {
return vle16ff_v_u16m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -691,7 +691,7 @@ vuint16m8_t test_vle16ff_v_u16m8_m (vbool2_t mask, vuint16m8_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
//
-vint32mf2_t test_vle32ff_v_i32mf2 (const int32_t *base, size_t *new_vl, size_t vl) {
+vint32mf2_t test_vle32ff_v_i32mf2(const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32mf2(base, new_vl, vl);
}
@@ -704,7 +704,7 @@ vint32mf2_t test_vle32ff_v_i32mf2 (const int32_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
//
-vint32m1_t test_vle32ff_v_i32m1 (const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m1_t test_vle32ff_v_i32m1(const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m1(base, new_vl, vl);
}
@@ -717,7 +717,7 @@ vint32m1_t test_vle32ff_v_i32m1 (const int32_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
//
-vint32m2_t test_vle32ff_v_i32m2 (const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m2_t test_vle32ff_v_i32m2(const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m2(base, new_vl, vl);
}
@@ -730,7 +730,7 @@ vint32m2_t test_vle32ff_v_i32m2 (const int32_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
//
-vint32m4_t test_vle32ff_v_i32m4 (const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m4_t test_vle32ff_v_i32m4(const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m4(base, new_vl, vl);
}
@@ -743,7 +743,7 @@ vint32m4_t test_vle32ff_v_i32m4 (const int32_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
//
-vint32m8_t test_vle32ff_v_i32m8 (const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m8_t test_vle32ff_v_i32m8(const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m8(base, new_vl, vl);
}
@@ -756,7 +756,7 @@ vint32m8_t test_vle32ff_v_i32m8 (const int32_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
//
-vuint32mf2_t test_vle32ff_v_u32mf2 (const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32mf2_t test_vle32ff_v_u32mf2(const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32mf2(base, new_vl, vl);
}
@@ -769,7 +769,7 @@ vuint32mf2_t test_vle32ff_v_u32mf2 (const uint32_t *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
//
-vuint32m1_t test_vle32ff_v_u32m1 (const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m1_t test_vle32ff_v_u32m1(const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m1(base, new_vl, vl);
}
@@ -782,7 +782,7 @@ vuint32m1_t test_vle32ff_v_u32m1 (const uint32_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
//
-vuint32m2_t test_vle32ff_v_u32m2 (const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m2_t test_vle32ff_v_u32m2(const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m2(base, new_vl, vl);
}
@@ -795,7 +795,7 @@ vuint32m2_t test_vle32ff_v_u32m2 (const uint32_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
//
-vuint32m4_t test_vle32ff_v_u32m4 (const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m4_t test_vle32ff_v_u32m4(const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m4(base, new_vl, vl);
}
@@ -808,7 +808,7 @@ vuint32m4_t test_vle32ff_v_u32m4 (const uint32_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
//
-vuint32m8_t test_vle32ff_v_u32m8 (const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m8_t test_vle32ff_v_u32m8(const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m8(base, new_vl, vl);
}
@@ -821,7 +821,7 @@ vuint32m8_t test_vle32ff_v_u32m8 (const uint32_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
//
-vfloat32mf2_t test_vle32ff_v_f32mf2 (const float *base, size_t *new_vl, size_t vl) {
+vfloat32mf2_t test_vle32ff_v_f32mf2(const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32mf2(base, new_vl, vl);
}
@@ -834,7 +834,7 @@ vfloat32mf2_t test_vle32ff_v_f32mf2 (const float *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP2]]
//
-vfloat32m1_t test_vle32ff_v_f32m1 (const float *base, size_t *new_vl, size_t vl) {
+vfloat32m1_t test_vle32ff_v_f32m1(const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m1(base, new_vl, vl);
}
@@ -847,7 +847,7 @@ vfloat32m1_t test_vle32ff_v_f32m1 (const float *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP2]]
//
-vfloat32m2_t test_vle32ff_v_f32m2 (const float *base, size_t *new_vl, size_t vl) {
+vfloat32m2_t test_vle32ff_v_f32m2(const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m2(base, new_vl, vl);
}
@@ -860,7 +860,7 @@ vfloat32m2_t test_vle32ff_v_f32m2 (const float *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP2]]
//
-vfloat32m4_t test_vle32ff_v_f32m4 (const float *base, size_t *new_vl, size_t vl) {
+vfloat32m4_t test_vle32ff_v_f32m4(const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m4(base, new_vl, vl);
}
@@ -873,7 +873,7 @@ vfloat32m4_t test_vle32ff_v_f32m4 (const float *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP2]]
//
-vfloat32m8_t test_vle32ff_v_f32m8 (const float *base, size_t *new_vl, size_t vl) {
+vfloat32m8_t test_vle32ff_v_f32m8(const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m8(base, new_vl, vl);
}
@@ -886,7 +886,7 @@ vfloat32m8_t test_vle32ff_v_f32m8 (const float *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
//
-vint32mf2_t test_vle32ff_v_i32mf2_m (vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
+vint32mf2_t test_vle32ff_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -899,7 +899,7 @@ vint32mf2_t test_vle32ff_v_i32mf2_m (vbool64_t mask, vint32mf2_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
//
-vint32m1_t test_vle32ff_v_i32m1_m (vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m1_t test_vle32ff_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -912,7 +912,7 @@ vint32m1_t test_vle32ff_v_i32m1_m (vbool32_t mask, vint32m1_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
//
-vint32m2_t test_vle32ff_v_i32m2_m (vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m2_t test_vle32ff_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -925,7 +925,7 @@ vint32m2_t test_vle32ff_v_i32m2_m (vbool16_t mask, vint32m2_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
//
-vint32m4_t test_vle32ff_v_i32m4_m (vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m4_t test_vle32ff_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -938,7 +938,7 @@ vint32m4_t test_vle32ff_v_i32m4_m (vbool8_t mask, vint32m4_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
//
-vint32m8_t test_vle32ff_v_i32m8_m (vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
+vint32m8_t test_vle32ff_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_i32m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -951,7 +951,7 @@ vint32m8_t test_vle32ff_v_i32m8_m (vbool4_t mask, vint32m8_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
//
-vuint32mf2_t test_vle32ff_v_u32mf2_m (vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32mf2_t test_vle32ff_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -964,7 +964,7 @@ vuint32mf2_t test_vle32ff_v_u32mf2_m (vbool64_t mask, vuint32mf2_t maskedoff, co
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP2]]
//
-vuint32m1_t test_vle32ff_v_u32m1_m (vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m1_t test_vle32ff_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -977,7 +977,7 @@ vuint32m1_t test_vle32ff_v_u32m1_m (vbool32_t mask, vuint32m1_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP2]]
//
-vuint32m2_t test_vle32ff_v_u32m2_m (vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m2_t test_vle32ff_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -990,7 +990,7 @@ vuint32m2_t test_vle32ff_v_u32m2_m (vbool16_t mask, vuint32m2_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP2]]
//
-vuint32m4_t test_vle32ff_v_u32m4_m (vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m4_t test_vle32ff_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1003,7 +1003,7 @@ vuint32m4_t test_vle32ff_v_u32m4_m (vbool8_t mask, vuint32m4_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP2]]
//
-vuint32m8_t test_vle32ff_v_u32m8_m (vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
+vuint32m8_t test_vle32ff_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) {
return vle32ff_v_u32m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1016,7 +1016,7 @@ vuint32m8_t test_vle32ff_v_u32m8_m (vbool4_t mask, vuint32m8_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
//
-vfloat32mf2_t test_vle32ff_v_f32mf2_m (vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
+vfloat32mf2_t test_vle32ff_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32mf2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1029,7 +1029,7 @@ vfloat32mf2_t test_vle32ff_v_f32mf2_m (vbool64_t mask, vfloat32mf2_t maskedoff,
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP2]]
//
-vfloat32m1_t test_vle32ff_v_f32m1_m (vbool32_t mask, vfloat32m1_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
+vfloat32m1_t test_vle32ff_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1042,7 +1042,7 @@ vfloat32m1_t test_vle32ff_v_f32m1_m (vbool32_t mask, vfloat32m1_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP2]]
//
-vfloat32m2_t test_vle32ff_v_f32m2_m (vbool16_t mask, vfloat32m2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
+vfloat32m2_t test_vle32ff_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1055,7 +1055,7 @@ vfloat32m2_t test_vle32ff_v_f32m2_m (vbool16_t mask, vfloat32m2_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP2]]
//
-vfloat32m4_t test_vle32ff_v_f32m4_m (vbool8_t mask, vfloat32m4_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
+vfloat32m4_t test_vle32ff_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1068,7 +1068,7 @@ vfloat32m4_t test_vle32ff_v_f32m4_m (vbool8_t mask, vfloat32m4_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP2]]
//
-vfloat32m8_t test_vle32ff_v_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
+vfloat32m8_t test_vle32ff_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) {
return vle32ff_v_f32m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1081,7 +1081,7 @@ vfloat32m8_t test_vle32ff_v_f32m8_m (vbool4_t mask, vfloat32m8_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
//
-vint64m1_t test_vle64ff_v_i64m1 (const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m1_t test_vle64ff_v_i64m1(const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m1(base, new_vl, vl);
}
@@ -1094,7 +1094,7 @@ vint64m1_t test_vle64ff_v_i64m1 (const int64_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
//
-vint64m2_t test_vle64ff_v_i64m2 (const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m2_t test_vle64ff_v_i64m2(const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m2(base, new_vl, vl);
}
@@ -1107,7 +1107,7 @@ vint64m2_t test_vle64ff_v_i64m2 (const int64_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
//
-vint64m4_t test_vle64ff_v_i64m4 (const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m4_t test_vle64ff_v_i64m4(const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m4(base, new_vl, vl);
}
@@ -1120,7 +1120,7 @@ vint64m4_t test_vle64ff_v_i64m4 (const int64_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
//
-vint64m8_t test_vle64ff_v_i64m8 (const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m8_t test_vle64ff_v_i64m8(const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m8(base, new_vl, vl);
}
@@ -1133,7 +1133,7 @@ vint64m8_t test_vle64ff_v_i64m8 (const int64_t *base, size_t *new_vl, size_t vl)
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
//
-vuint64m1_t test_vle64ff_v_u64m1 (const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m1_t test_vle64ff_v_u64m1(const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m1(base, new_vl, vl);
}
@@ -1146,7 +1146,7 @@ vuint64m1_t test_vle64ff_v_u64m1 (const uint64_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
//
-vuint64m2_t test_vle64ff_v_u64m2 (const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m2_t test_vle64ff_v_u64m2(const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m2(base, new_vl, vl);
}
@@ -1159,7 +1159,7 @@ vuint64m2_t test_vle64ff_v_u64m2 (const uint64_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
//
-vuint64m4_t test_vle64ff_v_u64m4 (const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m4_t test_vle64ff_v_u64m4(const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m4(base, new_vl, vl);
}
@@ -1172,7 +1172,7 @@ vuint64m4_t test_vle64ff_v_u64m4 (const uint64_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
//
-vuint64m8_t test_vle64ff_v_u64m8 (const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m8_t test_vle64ff_v_u64m8(const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m8(base, new_vl, vl);
}
@@ -1185,7 +1185,7 @@ vuint64m8_t test_vle64ff_v_u64m8 (const uint64_t *base, size_t *new_vl, size_t v
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP2]]
//
-vfloat64m1_t test_vle64ff_v_f64m1 (const double *base, size_t *new_vl, size_t vl) {
+vfloat64m1_t test_vle64ff_v_f64m1(const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m1(base, new_vl, vl);
}
@@ -1198,7 +1198,7 @@ vfloat64m1_t test_vle64ff_v_f64m1 (const double *base, size_t *new_vl, size_t vl
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP2]]
//
-vfloat64m2_t test_vle64ff_v_f64m2 (const double *base, size_t *new_vl, size_t vl) {
+vfloat64m2_t test_vle64ff_v_f64m2(const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m2(base, new_vl, vl);
}
@@ -1211,7 +1211,7 @@ vfloat64m2_t test_vle64ff_v_f64m2 (const double *base, size_t *new_vl, size_t vl
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP2]]
//
-vfloat64m4_t test_vle64ff_v_f64m4 (const double *base, size_t *new_vl, size_t vl) {
+vfloat64m4_t test_vle64ff_v_f64m4(const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m4(base, new_vl, vl);
}
@@ -1224,7 +1224,7 @@ vfloat64m4_t test_vle64ff_v_f64m4 (const double *base, size_t *new_vl, size_t vl
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP2]]
//
-vfloat64m8_t test_vle64ff_v_f64m8 (const double *base, size_t *new_vl, size_t vl) {
+vfloat64m8_t test_vle64ff_v_f64m8(const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m8(base, new_vl, vl);
}
@@ -1237,7 +1237,7 @@ vfloat64m8_t test_vle64ff_v_f64m8 (const double *base, size_t *new_vl, size_t vl
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
//
-vint64m1_t test_vle64ff_v_i64m1_m (vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m1_t test_vle64ff_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1250,7 +1250,7 @@ vint64m1_t test_vle64ff_v_i64m1_m (vbool64_t mask, vint64m1_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
//
-vint64m2_t test_vle64ff_v_i64m2_m (vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m2_t test_vle64ff_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1263,7 +1263,7 @@ vint64m2_t test_vle64ff_v_i64m2_m (vbool32_t mask, vint64m2_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
//
-vint64m4_t test_vle64ff_v_i64m4_m (vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m4_t test_vle64ff_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1276,7 +1276,7 @@ vint64m4_t test_vle64ff_v_i64m4_m (vbool16_t mask, vint64m4_t maskedoff, const i
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
//
-vint64m8_t test_vle64ff_v_i64m8_m (vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
+vint64m8_t test_vle64ff_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_i64m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1289,7 +1289,7 @@ vint64m8_t test_vle64ff_v_i64m8_m (vbool8_t mask, vint64m8_t maskedoff, const in
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP2]]
//
-vuint64m1_t test_vle64ff_v_u64m1_m (vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m1_t test_vle64ff_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1302,7 +1302,7 @@ vuint64m1_t test_vle64ff_v_u64m1_m (vbool64_t mask, vuint64m1_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP2]]
//
-vuint64m2_t test_vle64ff_v_u64m2_m (vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m2_t test_vle64ff_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1315,7 +1315,7 @@ vuint64m2_t test_vle64ff_v_u64m2_m (vbool32_t mask, vuint64m2_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP2]]
//
-vuint64m4_t test_vle64ff_v_u64m4_m (vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m4_t test_vle64ff_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1328,7 +1328,7 @@ vuint64m4_t test_vle64ff_v_u64m4_m (vbool16_t mask, vuint64m4_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP2]]
//
-vuint64m8_t test_vle64ff_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
+vuint64m8_t test_vle64ff_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) {
return vle64ff_v_u64m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1341,7 +1341,7 @@ vuint64m8_t test_vle64ff_v_u64m8_m (vbool8_t mask, vuint64m8_t maskedoff, const
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP2]]
//
-vfloat64m1_t test_vle64ff_v_f64m1_m (vbool64_t mask, vfloat64m1_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
+vfloat64m1_t test_vle64ff_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m1_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1354,7 +1354,7 @@ vfloat64m1_t test_vle64ff_v_f64m1_m (vbool64_t mask, vfloat64m1_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP2]]
//
-vfloat64m2_t test_vle64ff_v_f64m2_m (vbool32_t mask, vfloat64m2_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
+vfloat64m2_t test_vle64ff_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m2_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1367,7 +1367,7 @@ vfloat64m2_t test_vle64ff_v_f64m2_m (vbool32_t mask, vfloat64m2_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP2]]
//
-vfloat64m4_t test_vle64ff_v_f64m4_m (vbool16_t mask, vfloat64m4_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
+vfloat64m4_t test_vle64ff_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m4_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1380,7 +1380,7 @@ vfloat64m4_t test_vle64ff_v_f64m4_m (vbool16_t mask, vfloat64m4_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP2]]
//
-vfloat64m8_t test_vle64ff_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
+vfloat64m8_t test_vle64ff_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) {
return vle64ff_v_f64m8_m(mask, maskedoff, base, new_vl, vl);
}
@@ -1393,8 +1393,8 @@ vfloat64m8_t test_vle64ff_v_f64m8_m (vbool8_t mask, vfloat64m8_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP2]]
//
-vfloat16mf4_t test_vle16ff_v_f16mf4 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16mf4 (base, new_vl, vl);
+vfloat16mf4_t test_vle16ff_v_f16mf4(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16mf4(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2(
@@ -1406,8 +1406,8 @@ vfloat16mf4_t test_vle16ff_v_f16mf4 (const _Float16 *base, size_t *new_vl, size_
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP2]]
//
-vfloat16mf2_t test_vle16ff_v_f16mf2 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16mf2 (base, new_vl, vl);
+vfloat16mf2_t test_vle16ff_v_f16mf2(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16mf2(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m1(
@@ -1419,8 +1419,8 @@ vfloat16mf2_t test_vle16ff_v_f16mf2 (const _Float16 *base, size_t *new_vl, size_
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP2]]
//
-vfloat16m1_t test_vle16ff_v_f16m1 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m1 (base, new_vl, vl);
+vfloat16m1_t test_vle16ff_v_f16m1(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m1(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m2(
@@ -1432,8 +1432,8 @@ vfloat16m1_t test_vle16ff_v_f16m1 (const _Float16 *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
-vfloat16m2_t test_vle16ff_v_f16m2 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m2 (base, new_vl, vl);
+vfloat16m2_t test_vle16ff_v_f16m2(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m2(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m4(
@@ -1445,8 +1445,8 @@ vfloat16m2_t test_vle16ff_v_f16m2 (const _Float16 *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP2]]
//
-vfloat16m4_t test_vle16ff_v_f16m4 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m4 (base, new_vl, vl);
+vfloat16m4_t test_vle16ff_v_f16m4(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m4(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m8(
@@ -1458,8 +1458,8 @@ vfloat16m4_t test_vle16ff_v_f16m4 (const _Float16 *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP2]]
//
-vfloat16m8_t test_vle16ff_v_f16m8 (const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m8 (base, new_vl, vl);
+vfloat16m8_t test_vle16ff_v_f16m8(const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m8(base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16mf4_m(
@@ -1471,8 +1471,8 @@ vfloat16m8_t test_vle16ff_v_f16m8 (const _Float16 *base, size_t *new_vl, size_t
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP2]]
//
-vfloat16mf4_t test_vle16ff_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16mf4_m (mask, maskedoff, base, new_vl, vl);
+vfloat16mf4_t test_vle16ff_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16mf4_m(mask, maskedoff, base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16mf2_m(
@@ -1484,8 +1484,8 @@ vfloat16mf4_t test_vle16ff_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP2]]
//
-vfloat16mf2_t test_vle16ff_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16mf2_m (mask, maskedoff, base, new_vl, vl);
+vfloat16mf2_t test_vle16ff_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16mf2_m(mask, maskedoff, base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m1_m(
@@ -1497,8 +1497,8 @@ vfloat16mf2_t test_vle16ff_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP2]]
//
-vfloat16m1_t test_vle16ff_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m1_m (mask, maskedoff, base, new_vl, vl);
+vfloat16m1_t test_vle16ff_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m1_m(mask, maskedoff, base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m2_m(
@@ -1510,8 +1510,8 @@ vfloat16m1_t test_vle16ff_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, con
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
-vfloat16m2_t test_vle16ff_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m2_m (mask, maskedoff, base, new_vl, vl);
+vfloat16m2_t test_vle16ff_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m2_m(mask, maskedoff, base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m4_m(
@@ -1523,8 +1523,8 @@ vfloat16m2_t test_vle16ff_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP2]]
//
-vfloat16m4_t test_vle16ff_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m4_m (mask, maskedoff, base, new_vl, vl);
+vfloat16m4_t test_vle16ff_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m4_m(mask, maskedoff, base, new_vl, vl);
}
// CHECK-RV64-LABEL: @test_vle16ff_v_f16m8_m(
@@ -1536,6 +1536,240 @@ vfloat16m4_t test_vle16ff_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, cons
// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP2]]
//
-vfloat16m8_t test_vle16ff_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
- return vle16ff_v_f16m8_m (mask, maskedoff, base, new_vl, vl);
+vfloat16m8_t test_vle16ff_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) {
+ return vle16ff_v_f16m8_m(mask, maskedoff, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_tu(merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_tu(merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_tu(merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_ta(const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_ta(base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_ta(const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_ta(base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_ta(const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_ta(base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_tuma(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_tuma(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_tuma(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_tumu(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_tumu(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_tumu(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_tama(vbool64_t mask, const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_tama(mask, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_tama(mask, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_tama(vbool64_t mask, const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_tama(mask, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vint32mf2_t test_vle32ff_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_i32mf2_tamu(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x i32>, i64 } @llvm.riscv.vleff.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x i32>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP2]]
+//
+vuint32mf2_t test_vle32ff_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_u32mf2_tamu(mask, merge, base, new_vl, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle32ff_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call { <vscale x 1 x float>, i64 } @llvm.riscv.vleff.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 0
+// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 1 x float>, i64 } [[TMP1]], 1
+// CHECK-RV64-NEXT: store i64 [[TMP3]], i64* [[NEW_VL:%.*]], align 8
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP2]]
+//
+vfloat32mf2_t test_vle32ff_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, size_t *new_vl, size_t vl) {
+ return vle32ff_v_f32mf2_tamu(mask, merge, base, new_vl, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
index 6bcc401f25926..98b06b341d1e9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
@@ -3832,8 +3832,8 @@ vfloat64m8_t test_vloxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
- return vloxei8_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vloxei8_v_f16mf4(const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
+ return vloxei8_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf2(
@@ -3842,8 +3842,8 @@ vfloat16mf4_t test_vloxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, s
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
- return vloxei8_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vloxei8_v_f16mf2(const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
+ return vloxei8_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m1(
@@ -3852,8 +3852,8 @@ vfloat16mf2_t test_vloxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, s
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
- return vloxei8_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vloxei8_v_f16m1(const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
+ return vloxei8_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m2(
@@ -3862,8 +3862,8 @@ vfloat16m1_t test_vloxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, siz
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) {
- return vloxei8_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vloxei8_v_f16m2(const _Float16 *base, vuint8m1_t bindex, size_t vl) {
+ return vloxei8_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m4(
@@ -3872,8 +3872,8 @@ vfloat16m2_t test_vloxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) {
- return vloxei8_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vloxei8_v_f16m4(const _Float16 *base, vuint8m2_t bindex, size_t vl) {
+ return vloxei8_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m8(
@@ -3882,8 +3882,8 @@ vfloat16m4_t test_vloxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vloxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) {
- return vloxei8_v_f16m8 (base, bindex, vl);
+vfloat16m8_t test_vloxei8_v_f16m8(const _Float16 *base, vuint8m4_t bindex, size_t vl) {
+ return vloxei8_v_f16m8(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf4(
@@ -3892,8 +3892,8 @@ vfloat16m8_t test_vloxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
- return vloxei16_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vloxei16_v_f16mf4(const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
+ return vloxei16_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf2(
@@ -3902,8 +3902,8 @@ vfloat16mf4_t test_vloxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
- return vloxei16_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vloxei16_v_f16mf2(const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
+ return vloxei16_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m1(
@@ -3912,8 +3912,8 @@ vfloat16mf2_t test_vloxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) {
- return vloxei16_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vloxei16_v_f16m1(const _Float16 *base, vuint16m1_t bindex, size_t vl) {
+ return vloxei16_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m2(
@@ -3922,8 +3922,8 @@ vfloat16m1_t test_vloxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) {
- return vloxei16_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vloxei16_v_f16m2(const _Float16 *base, vuint16m2_t bindex, size_t vl) {
+ return vloxei16_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m4(
@@ -3932,8 +3932,8 @@ vfloat16m2_t test_vloxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) {
- return vloxei16_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vloxei16_v_f16m4(const _Float16 *base, vuint16m4_t bindex, size_t vl) {
+ return vloxei16_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m8(
@@ -3942,8 +3942,8 @@ vfloat16m4_t test_vloxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vloxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) {
- return vloxei16_v_f16m8 (base, bindex, vl);
+vfloat16m8_t test_vloxei16_v_f16m8(const _Float16 *base, vuint16m8_t bindex, size_t vl) {
+ return vloxei16_v_f16m8(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf4(
@@ -3952,8 +3952,8 @@ vfloat16m8_t test_vloxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
- return vloxei32_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vloxei32_v_f16mf4(const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf2(
@@ -3962,8 +3962,8 @@ vfloat16mf4_t test_vloxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) {
- return vloxei32_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vloxei32_v_f16mf2(const _Float16 *base, vuint32m1_t bindex, size_t vl) {
+ return vloxei32_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m1(
@@ -3972,8 +3972,8 @@ vfloat16mf2_t test_vloxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) {
- return vloxei32_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vloxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return vloxei32_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m2(
@@ -3982,8 +3982,8 @@ vfloat16m1_t test_vloxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) {
- return vloxei32_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vloxei32_v_f16m2(const _Float16 *base, vuint32m4_t bindex, size_t vl) {
+ return vloxei32_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m4(
@@ -3992,8 +3992,8 @@ vfloat16m2_t test_vloxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) {
- return vloxei32_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vloxei32_v_f16m4(const _Float16 *base, vuint32m8_t bindex, size_t vl) {
+ return vloxei32_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf4(
@@ -4002,8 +4002,8 @@ vfloat16m4_t test_vloxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) {
- return vloxei64_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vloxei64_v_f16mf4(const _Float16 *base, vuint64m1_t bindex, size_t vl) {
+ return vloxei64_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf2(
@@ -4012,8 +4012,8 @@ vfloat16mf4_t test_vloxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) {
- return vloxei64_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vloxei64_v_f16mf2(const _Float16 *base, vuint64m2_t bindex, size_t vl) {
+ return vloxei64_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m1(
@@ -4022,8 +4022,8 @@ vfloat16mf2_t test_vloxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) {
- return vloxei64_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vloxei64_v_f16m1(const _Float16 *base, vuint64m4_t bindex, size_t vl) {
+ return vloxei64_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m2(
@@ -4032,8 +4032,8 @@ vfloat16m1_t test_vloxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) {
- return vloxei64_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vloxei64_v_f16m2(const _Float16 *base, vuint64m8_t bindex, size_t vl) {
+ return vloxei64_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf4_m(
@@ -4042,8 +4042,8 @@ vfloat16m2_t test_vloxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei8_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
- return vloxei8_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vloxei8_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
+ return vloxei8_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16mf2_m(
@@ -4052,8 +4052,8 @@ vfloat16mf4_t test_vloxei8_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei8_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
- return vloxei8_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vloxei8_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
+ return vloxei8_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m1_m(
@@ -4062,8 +4062,8 @@ vfloat16mf2_t test_vloxei8_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei8_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
- return vloxei8_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vloxei8_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
+ return vloxei8_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m2_m(
@@ -4072,8 +4072,8 @@ vfloat16m1_t test_vloxei8_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei8_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint8m1_t bindex, size_t vl) {
- return vloxei8_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vloxei8_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint8m1_t bindex, size_t vl) {
+ return vloxei8_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m4_m(
@@ -4082,8 +4082,8 @@ vfloat16m2_t test_vloxei8_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei8_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint8m2_t bindex, size_t vl) {
- return vloxei8_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vloxei8_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint8m2_t bindex, size_t vl) {
+ return vloxei8_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei8_v_f16m8_m(
@@ -4092,8 +4092,8 @@ vfloat16m4_t test_vloxei8_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vloxei8_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint8m4_t bindex, size_t vl) {
- return vloxei8_v_f16m8_m (mask, maskedoff, base, bindex, vl);
+vfloat16m8_t test_vloxei8_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint8m4_t bindex, size_t vl) {
+ return vloxei8_v_f16m8_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf4_m(
@@ -4102,8 +4102,8 @@ vfloat16m8_t test_vloxei8_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
- return vloxei16_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vloxei16_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
+ return vloxei16_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16mf2_m(
@@ -4112,8 +4112,8 @@ vfloat16mf4_t test_vloxei16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
- return vloxei16_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vloxei16_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
+ return vloxei16_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m1_m(
@@ -4122,8 +4122,8 @@ vfloat16mf2_t test_vloxei16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint16m1_t bindex, size_t vl) {
- return vloxei16_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vloxei16_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint16m1_t bindex, size_t vl) {
+ return vloxei16_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m2_m(
@@ -4132,8 +4132,8 @@ vfloat16m1_t test_vloxei16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint16m2_t bindex, size_t vl) {
- return vloxei16_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vloxei16_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint16m2_t bindex, size_t vl) {
+ return vloxei16_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m4_m(
@@ -4142,8 +4142,8 @@ vfloat16m2_t test_vloxei16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint16m4_t bindex, size_t vl) {
- return vloxei16_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vloxei16_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint16m4_t bindex, size_t vl) {
+ return vloxei16_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei16_v_f16m8_m(
@@ -4152,8 +4152,8 @@ vfloat16m4_t test_vloxei16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vloxei16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint16m8_t bindex, size_t vl) {
- return vloxei16_v_f16m8_m (mask, maskedoff, base, bindex, vl);
+vfloat16m8_t test_vloxei16_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint16m8_t bindex, size_t vl) {
+ return vloxei16_v_f16m8_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf4_m(
@@ -4162,8 +4162,8 @@ vfloat16m8_t test_vloxei16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei32_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
- return vloxei32_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vloxei32_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16mf2_m(
@@ -4172,8 +4172,8 @@ vfloat16mf4_t test_vloxei32_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei32_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint32m1_t bindex, size_t vl) {
- return vloxei32_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vloxei32_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint32m1_t bindex, size_t vl) {
+ return vloxei32_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m1_m(
@@ -4182,8 +4182,8 @@ vfloat16mf2_t test_vloxei32_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei32_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint32m2_t bindex, size_t vl) {
- return vloxei32_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vloxei32_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return vloxei32_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m2_m(
@@ -4192,8 +4192,8 @@ vfloat16m1_t test_vloxei32_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei32_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint32m4_t bindex, size_t vl) {
- return vloxei32_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vloxei32_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint32m4_t bindex, size_t vl) {
+ return vloxei32_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei32_v_f16m4_m(
@@ -4202,8 +4202,8 @@ vfloat16m2_t test_vloxei32_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vloxei32_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint32m8_t bindex, size_t vl) {
- return vloxei32_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vloxei32_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint32m8_t bindex, size_t vl) {
+ return vloxei32_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf4_m(
@@ -4212,8 +4212,8 @@ vfloat16m4_t test_vloxei32_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vloxei64_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint64m1_t bindex, size_t vl) {
- return vloxei64_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vloxei64_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint64m1_t bindex, size_t vl) {
+ return vloxei64_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16mf2_m(
@@ -4222,8 +4222,8 @@ vfloat16mf4_t test_vloxei64_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vloxei64_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint64m2_t bindex, size_t vl) {
- return vloxei64_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vloxei64_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint64m2_t bindex, size_t vl) {
+ return vloxei64_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m1_m(
@@ -4232,8 +4232,8 @@ vfloat16mf2_t test_vloxei64_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vloxei64_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint64m4_t bindex, size_t vl) {
- return vloxei64_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vloxei64_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint64m4_t bindex, size_t vl) {
+ return vloxei64_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vloxei64_v_f16m2_m(
@@ -4242,6 +4242,186 @@ vfloat16m1_t test_vloxei64_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vloxei64_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint64m8_t bindex, size_t vl) {
- return vloxei64_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vloxei64_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint64m8_t bindex, size_t vl) {
+ return vloxei64_v_f16m2_m(mask, maskedoff, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_ta(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_ta(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_ta(const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tama(vbool64_t mask, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tama(vbool64_t mask, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vloxei32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_i32mf2_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vloxei32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_u32mf2_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vloxei32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vloxei32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vloxei32_v_f32mf2_tamu(mask, merge, base, bindex, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
index ceb89fd39cf7b..a99c6990f0988 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
@@ -1227,8 +1227,8 @@ vfloat64m8_t test_vlse64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vlse.nxv1f16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vlse16_v_f16mf4 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16mf4 (base, bstride, vl);
+vfloat16mf4_t test_vlse16_v_f16mf4(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16mf4(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf2(
@@ -1237,8 +1237,8 @@ vfloat16mf4_t test_vlse16_v_f16mf4 (const _Float16 *base, ptr
diff _t bstride, siz
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vlse.nxv2f16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vlse16_v_f16mf2 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16mf2 (base, bstride, vl);
+vfloat16mf2_t test_vlse16_v_f16mf2(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16mf2(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m1(
@@ -1247,8 +1247,8 @@ vfloat16mf2_t test_vlse16_v_f16mf2 (const _Float16 *base, ptr
diff _t bstride, siz
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vlse.nxv4f16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vlse16_v_f16m1 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m1 (base, bstride, vl);
+vfloat16m1_t test_vlse16_v_f16m1(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m1(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m2(
@@ -1257,8 +1257,8 @@ vfloat16m1_t test_vlse16_v_f16m1 (const _Float16 *base, ptr
diff _t bstride, size_
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vlse.nxv8f16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vlse16_v_f16m2 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m2 (base, bstride, vl);
+vfloat16m2_t test_vlse16_v_f16m2(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m2(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m4(
@@ -1267,8 +1267,8 @@ vfloat16m2_t test_vlse16_v_f16m2 (const _Float16 *base, ptr
diff _t bstride, size_
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vlse.nxv16f16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vlse16_v_f16m4 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m4 (base, bstride, vl);
+vfloat16m4_t test_vlse16_v_f16m4(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m4(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m8(
@@ -1277,8 +1277,8 @@ vfloat16m4_t test_vlse16_v_f16m4 (const _Float16 *base, ptr
diff _t bstride, size_
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vlse.nxv32f16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vlse16_v_f16m8 (const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m8 (base, bstride, vl);
+vfloat16m8_t test_vlse16_v_f16m8(const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m8(base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf4_m(
@@ -1287,8 +1287,8 @@ vfloat16m8_t test_vlse16_v_f16m8 (const _Float16 *base, ptr
diff _t bstride, size_
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vlse.mask.nxv1f16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vlse16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16mf4_m (mask, maskedoff, base, bstride, vl);
+vfloat16mf4_t test_vlse16_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16mf4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16mf2_m(
@@ -1297,8 +1297,8 @@ vfloat16mf4_t test_vlse16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, c
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vlse.mask.nxv2f16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vlse16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16mf2_m (mask, maskedoff, base, bstride, vl);
+vfloat16mf2_t test_vlse16_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16mf2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m1_m(
@@ -1307,8 +1307,8 @@ vfloat16mf2_t test_vlse16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, c
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vlse.mask.nxv4f16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vlse16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m1_m (mask, maskedoff, base, bstride, vl);
+vfloat16m1_t test_vlse16_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m1_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m2_m(
@@ -1317,8 +1317,8 @@ vfloat16m1_t test_vlse16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vlse.mask.nxv8f16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vlse16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m2_m (mask, maskedoff, base, bstride, vl);
+vfloat16m2_t test_vlse16_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m2_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m4_m(
@@ -1327,8 +1327,8 @@ vfloat16m2_t test_vlse16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vlse.mask.nxv16f16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vlse16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m4_m (mask, maskedoff, base, bstride, vl);
+vfloat16m4_t test_vlse16_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m4_m(mask, maskedoff, base, bstride, vl);
}
// CHECK-RV64-LABEL: @test_vlse16_v_f16m8_m(
@@ -1337,6 +1337,186 @@ vfloat16m4_t test_vlse16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vlse.mask.nxv32f16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vlse16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
- return vlse16_v_f16m8_m (mask, maskedoff, base, bstride, vl);
+vfloat16m8_t test_vlse16_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, ptr
diff _t bstride, size_t vl) {
+ return vlse16_v_f16m8_m(mask, maskedoff, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_tu(merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_ta(const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_ta(base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_ta(const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_ta(base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_ta(const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_ta(base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_tuma(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_tumu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tama(vbool64_t mask, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_tama(mask, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_tama(mask, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tama(vbool64_t mask, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_tama(mask, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vlse32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_i32mf2_tamu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vlse32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_u32mf2_tamu(mask, merge, base, bstride, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlse32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vlse.mask.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], i64 [[BSTRIDE:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vlse32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, ptr
diff _t bstride, size_t vl) {
+ return vlse32_v_f32mf2_tamu(mask, merge, base, bstride, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
index 763e1858d276c..7796920273dc5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
@@ -3832,8 +3832,8 @@ vfloat64m8_t test_vluxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
- return vluxei8_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vluxei8_v_f16mf4(const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
+ return vluxei8_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf2(
@@ -3842,8 +3842,8 @@ vfloat16mf4_t test_vluxei8_v_f16mf4 (const _Float16 *base, vuint8mf8_t bindex, s
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
- return vluxei8_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vluxei8_v_f16mf2(const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
+ return vluxei8_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m1(
@@ -3852,8 +3852,8 @@ vfloat16mf2_t test_vluxei8_v_f16mf2 (const _Float16 *base, vuint8mf4_t bindex, s
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
- return vluxei8_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vluxei8_v_f16m1(const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
+ return vluxei8_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m2(
@@ -3862,8 +3862,8 @@ vfloat16m1_t test_vluxei8_v_f16m1 (const _Float16 *base, vuint8mf2_t bindex, siz
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size_t vl) {
- return vluxei8_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vluxei8_v_f16m2(const _Float16 *base, vuint8m1_t bindex, size_t vl) {
+ return vluxei8_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m4(
@@ -3872,8 +3872,8 @@ vfloat16m2_t test_vluxei8_v_f16m2 (const _Float16 *base, vuint8m1_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size_t vl) {
- return vluxei8_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vluxei8_v_f16m4(const _Float16 *base, vuint8m2_t bindex, size_t vl) {
+ return vluxei8_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m8(
@@ -3882,8 +3882,8 @@ vfloat16m4_t test_vluxei8_v_f16m4 (const _Float16 *base, vuint8m2_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vluxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size_t vl) {
- return vluxei8_v_f16m8 (base, bindex, vl);
+vfloat16m8_t test_vluxei8_v_f16m8(const _Float16 *base, vuint8m4_t bindex, size_t vl) {
+ return vluxei8_v_f16m8(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf4(
@@ -3892,8 +3892,8 @@ vfloat16m8_t test_vluxei8_v_f16m8 (const _Float16 *base, vuint8m4_t bindex, size
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
- return vluxei16_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vluxei16_v_f16mf4(const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
+ return vluxei16_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf2(
@@ -3902,8 +3902,8 @@ vfloat16mf4_t test_vluxei16_v_f16mf4 (const _Float16 *base, vuint16mf4_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
- return vluxei16_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vluxei16_v_f16mf2(const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
+ return vluxei16_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m1(
@@ -3912,8 +3912,8 @@ vfloat16mf2_t test_vluxei16_v_f16mf2 (const _Float16 *base, vuint16mf2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, size_t vl) {
- return vluxei16_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vluxei16_v_f16m1(const _Float16 *base, vuint16m1_t bindex, size_t vl) {
+ return vluxei16_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m2(
@@ -3922,8 +3922,8 @@ vfloat16m1_t test_vluxei16_v_f16m1 (const _Float16 *base, vuint16m1_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, size_t vl) {
- return vluxei16_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vluxei16_v_f16m2(const _Float16 *base, vuint16m2_t bindex, size_t vl) {
+ return vluxei16_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m4(
@@ -3932,8 +3932,8 @@ vfloat16m2_t test_vluxei16_v_f16m2 (const _Float16 *base, vuint16m2_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, size_t vl) {
- return vluxei16_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vluxei16_v_f16m4(const _Float16 *base, vuint16m4_t bindex, size_t vl) {
+ return vluxei16_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m8(
@@ -3942,8 +3942,8 @@ vfloat16m4_t test_vluxei16_v_f16m4 (const _Float16 *base, vuint16m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16.i64(<vscale x 32 x half> undef, <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vluxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, size_t vl) {
- return vluxei16_v_f16m8 (base, bindex, vl);
+vfloat16m8_t test_vluxei16_v_f16m8(const _Float16 *base, vuint16m8_t bindex, size_t vl) {
+ return vluxei16_v_f16m8(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf4(
@@ -3952,8 +3952,8 @@ vfloat16m8_t test_vluxei16_v_f16m8 (const _Float16 *base, vuint16m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
- return vluxei32_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vluxei32_v_f16mf4(const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf2(
@@ -3962,8 +3962,8 @@ vfloat16mf4_t test_vluxei32_v_f16mf4 (const _Float16 *base, vuint32mf2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex, size_t vl) {
- return vluxei32_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vluxei32_v_f16mf2(const _Float16 *base, vuint32m1_t bindex, size_t vl) {
+ return vluxei32_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m1(
@@ -3972,8 +3972,8 @@ vfloat16mf2_t test_vluxei32_v_f16mf2 (const _Float16 *base, vuint32m1_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, size_t vl) {
- return vluxei32_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vluxei32_v_f16m1(const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return vluxei32_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m2(
@@ -3982,8 +3982,8 @@ vfloat16m1_t test_vluxei32_v_f16m1 (const _Float16 *base, vuint32m2_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, size_t vl) {
- return vluxei32_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vluxei32_v_f16m2(const _Float16 *base, vuint32m4_t bindex, size_t vl) {
+ return vluxei32_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m4(
@@ -3992,8 +3992,8 @@ vfloat16m2_t test_vluxei32_v_f16m2 (const _Float16 *base, vuint32m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32.i64(<vscale x 16 x half> undef, <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, size_t vl) {
- return vluxei32_v_f16m4 (base, bindex, vl);
+vfloat16m4_t test_vluxei32_v_f16m4(const _Float16 *base, vuint32m8_t bindex, size_t vl) {
+ return vluxei32_v_f16m4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf4(
@@ -4002,8 +4002,8 @@ vfloat16m4_t test_vluxei32_v_f16m4 (const _Float16 *base, vuint32m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i64.i64(<vscale x 1 x half> undef, <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex, size_t vl) {
- return vluxei64_v_f16mf4 (base, bindex, vl);
+vfloat16mf4_t test_vluxei64_v_f16mf4(const _Float16 *base, vuint64m1_t bindex, size_t vl) {
+ return vluxei64_v_f16mf4(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf2(
@@ -4012,8 +4012,8 @@ vfloat16mf4_t test_vluxei64_v_f16mf4 (const _Float16 *base, vuint64m1_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i64.i64(<vscale x 2 x half> undef, <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex, size_t vl) {
- return vluxei64_v_f16mf2 (base, bindex, vl);
+vfloat16mf2_t test_vluxei64_v_f16mf2(const _Float16 *base, vuint64m2_t bindex, size_t vl) {
+ return vluxei64_v_f16mf2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m1(
@@ -4022,8 +4022,8 @@ vfloat16mf2_t test_vluxei64_v_f16mf2 (const _Float16 *base, vuint64m2_t bindex,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i64.i64(<vscale x 4 x half> undef, <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, size_t vl) {
- return vluxei64_v_f16m1 (base, bindex, vl);
+vfloat16m1_t test_vluxei64_v_f16m1(const _Float16 *base, vuint64m4_t bindex, size_t vl) {
+ return vluxei64_v_f16m1(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m2(
@@ -4032,8 +4032,8 @@ vfloat16m1_t test_vluxei64_v_f16m1 (const _Float16 *base, vuint64m4_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i64.i64(<vscale x 8 x half> undef, <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, size_t vl) {
- return vluxei64_v_f16m2 (base, bindex, vl);
+vfloat16m2_t test_vluxei64_v_f16m2(const _Float16 *base, vuint64m8_t bindex, size_t vl) {
+ return vluxei64_v_f16m2(base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf4_m(
@@ -4042,8 +4042,8 @@ vfloat16m2_t test_vluxei64_v_f16m2 (const _Float16 *base, vuint64m8_t bindex, si
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei8_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
- return vluxei8_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vluxei8_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint8mf8_t bindex, size_t vl) {
+ return vluxei8_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16mf2_m(
@@ -4052,19 +4052,18 @@ vfloat16mf4_t test_vluxei8_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei8_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
- return vluxei8_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vluxei8_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint8mf4_t bindex, size_t vl) {
+ return vluxei8_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
-
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m1_m(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei8_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
- return vluxei8_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vluxei8_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint8mf2_t bindex, size_t vl) {
+ return vluxei8_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m2_m(
@@ -4073,8 +4072,8 @@ vfloat16m1_t test_vluxei8_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei8_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint8m1_t bindex, size_t vl) {
- return vluxei8_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vluxei8_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint8m1_t bindex, size_t vl) {
+ return vluxei8_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m4_m(
@@ -4083,8 +4082,8 @@ vfloat16m2_t test_vluxei8_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei8_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint8m2_t bindex, size_t vl) {
- return vluxei8_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vluxei8_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint8m2_t bindex, size_t vl) {
+ return vluxei8_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei8_v_f16m8_m(
@@ -4093,8 +4092,8 @@ vfloat16m4_t test_vluxei8_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vluxei8_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint8m4_t bindex, size_t vl) {
- return vluxei8_v_f16m8_m (mask, maskedoff, base, bindex, vl);
+vfloat16m8_t test_vluxei8_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint8m4_t bindex, size_t vl) {
+ return vluxei8_v_f16m8_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf4_m(
@@ -4103,8 +4102,8 @@ vfloat16m8_t test_vluxei8_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, cons
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
- return vluxei16_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vluxei16_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint16mf4_t bindex, size_t vl) {
+ return vluxei16_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16mf2_m(
@@ -4113,8 +4112,8 @@ vfloat16mf4_t test_vluxei16_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
- return vluxei16_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vluxei16_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint16mf2_t bindex, size_t vl) {
+ return vluxei16_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m1_m(
@@ -4123,8 +4122,8 @@ vfloat16mf2_t test_vluxei16_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint16m1_t bindex, size_t vl) {
- return vluxei16_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vluxei16_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint16m1_t bindex, size_t vl) {
+ return vluxei16_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m2_m(
@@ -4133,8 +4132,8 @@ vfloat16m1_t test_vluxei16_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint16m2_t bindex, size_t vl) {
- return vluxei16_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vluxei16_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint16m2_t bindex, size_t vl) {
+ return vluxei16_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m4_m(
@@ -4143,8 +4142,8 @@ vfloat16m2_t test_vluxei16_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint16m4_t bindex, size_t vl) {
- return vluxei16_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vluxei16_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint16m4_t bindex, size_t vl) {
+ return vluxei16_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei16_v_f16m8_m(
@@ -4153,8 +4152,8 @@ vfloat16m4_t test_vluxei16_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16.i64(<vscale x 32 x half> [[MASKEDOFF:%.*]], <vscale x 32 x half>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP1]]
//
-vfloat16m8_t test_vluxei16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint16m8_t bindex, size_t vl) {
- return vluxei16_v_f16m8_m (mask, maskedoff, base, bindex, vl);
+vfloat16m8_t test_vluxei16_v_f16m8_m(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, vuint16m8_t bindex, size_t vl) {
+ return vluxei16_v_f16m8_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf4_m(
@@ -4163,8 +4162,8 @@ vfloat16m8_t test_vluxei16_v_f16m8_m (vbool2_t mask, vfloat16m8_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei32_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
- return vluxei32_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vluxei32_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16mf2_m(
@@ -4173,8 +4172,8 @@ vfloat16mf4_t test_vluxei32_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei32_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint32m1_t bindex, size_t vl) {
- return vluxei32_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vluxei32_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint32m1_t bindex, size_t vl) {
+ return vluxei32_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m1_m(
@@ -4183,8 +4182,8 @@ vfloat16mf2_t test_vluxei32_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei32_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint32m2_t bindex, size_t vl) {
- return vluxei32_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vluxei32_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint32m2_t bindex, size_t vl) {
+ return vluxei32_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m2_m(
@@ -4193,8 +4192,8 @@ vfloat16m1_t test_vluxei32_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei32_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint32m4_t bindex, size_t vl) {
- return vluxei32_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vluxei32_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint32m4_t bindex, size_t vl) {
+ return vluxei32_v_f16m2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei32_v_f16m4_m(
@@ -4203,8 +4202,8 @@ vfloat16m2_t test_vluxei32_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32.i64(<vscale x 16 x half> [[MASKEDOFF:%.*]], <vscale x 16 x half>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP1]]
//
-vfloat16m4_t test_vluxei32_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint32m8_t bindex, size_t vl) {
- return vluxei32_v_f16m4_m (mask, maskedoff, base, bindex, vl);
+vfloat16m4_t test_vluxei32_v_f16m4_m(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, vuint32m8_t bindex, size_t vl) {
+ return vluxei32_v_f16m4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf4_m(
@@ -4213,8 +4212,8 @@ vfloat16m4_t test_vluxei32_v_f16m4_m (vbool4_t mask, vfloat16m4_t maskedoff, con
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i64.i64(<vscale x 1 x half> [[MASKEDOFF:%.*]], <vscale x 1 x half>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP1]]
//
-vfloat16mf4_t test_vluxei64_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint64m1_t bindex, size_t vl) {
- return vluxei64_v_f16mf4_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf4_t test_vluxei64_v_f16mf4_m(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, vuint64m1_t bindex, size_t vl) {
+ return vluxei64_v_f16mf4_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16mf2_m(
@@ -4223,8 +4222,8 @@ vfloat16mf4_t test_vluxei64_v_f16mf4_m (vbool64_t mask, vfloat16mf4_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i64.i64(<vscale x 2 x half> [[MASKEDOFF:%.*]], <vscale x 2 x half>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP1]]
//
-vfloat16mf2_t test_vluxei64_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint64m2_t bindex, size_t vl) {
- return vluxei64_v_f16mf2_m (mask, maskedoff, base, bindex, vl);
+vfloat16mf2_t test_vluxei64_v_f16mf2_m(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, vuint64m2_t bindex, size_t vl) {
+ return vluxei64_v_f16mf2_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m1_m(
@@ -4233,8 +4232,8 @@ vfloat16mf2_t test_vluxei64_v_f16mf2_m (vbool32_t mask, vfloat16mf2_t maskedoff,
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i64.i64(<vscale x 4 x half> [[MASKEDOFF:%.*]], <vscale x 4 x half>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP1]]
//
-vfloat16m1_t test_vluxei64_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint64m4_t bindex, size_t vl) {
- return vluxei64_v_f16m1_m (mask, maskedoff, base, bindex, vl);
+vfloat16m1_t test_vluxei64_v_f16m1_m(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, vuint64m4_t bindex, size_t vl) {
+ return vluxei64_v_f16m1_m(mask, maskedoff, base, bindex, vl);
}
// CHECK-RV64-LABEL: @test_vluxei64_v_f16m2_m(
@@ -4243,6 +4242,186 @@ vfloat16m1_t test_vluxei64_v_f16m1_m (vbool16_t mask, vfloat16m1_t maskedoff, co
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i64.i64(<vscale x 8 x half> [[MASKEDOFF:%.*]], <vscale x 8 x half>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
-vfloat16m2_t test_vluxei64_v_f16m2_m (vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint64m8_t bindex, size_t vl) {
- return vluxei64_v_f16m2_m (mask, maskedoff, base, bindex, vl);
+vfloat16m2_t test_vluxei64_v_f16m2_m(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, vuint64m8_t bindex, size_t vl) {
+ return vluxei64_v_f16m2_m(mask, maskedoff, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tu(vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tu(vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tu(vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_tu(merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_ta(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_ta(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_ta(const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_ta(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tuma(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tuma(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tuma(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tuma(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_tuma(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tumu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tumu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_tumu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tama(vbool64_t mask, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tama(vbool64_t mask, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tama(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> undef, <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 3)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tama(vbool64_t mask, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_tama(mask, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vint32mf2_t test_vluxei32_v_i32mf2_tamu(vbool64_t mask, vint32mf2_t merge, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_i32mf2_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
+//
+vuint32mf2_t test_vluxei32_v_u32mf2_tamu(vbool64_t mask, vuint32mf2_t merge, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_u32mf2_tamu(mask, merge, base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_tamu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 1)
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
+//
+vfloat32mf2_t test_vluxei32_v_f32mf2_tamu(vbool64_t mask, vfloat32mf2_t merge, const float *base, vuint32mf2_t bindex, size_t vl) {
+ return vluxei32_v_f32mf2_tamu(mask, merge, base, bindex, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
index 6814b411ef9cd..973d268b45315 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
@@ -1696,3 +1696,129 @@ vfloat16m4_t test_vmv_v_v_f16m4 (vfloat16m4_t src, size_t vl) {
vfloat16m8_t test_vmv_v_v_f16m8 (vfloat16m8_t src, size_t vl) {
return vmv_v_v_f16m8(src, vl);
}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_v_i32mf2_tu (vint32mf2_t merge, vint32mf2_t src, size_t vl) {
+ return vmv_v_v_i32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_x_i32mf2_tu (vint32mf2_t merge, int32_t src, size_t vl) {
+ return vmv_v_x_i32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_v_u32mf2_tu (vuint32mf2_t merge, vuint32mf2_t src, size_t vl) {
+ return vmv_v_v_u32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_x_u32mf2_tu (vuint32mf2_t merge, uint32_t src, size_t vl) {
+ return vmv_v_x_u32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_v_i32mf2_ta (vint32mf2_t src, size_t vl) {
+ return vmv_v_v_i32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_v_x_i32mf2_ta (int32_t src, size_t vl) {
+ return vmv_v_x_i32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32.i64(<vscale x 1 x i32> undef, <vscale x 1 x i32> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_v_u32mf2_ta (vuint32mf2_t src, size_t vl) {
+ return vmv_v_v_u32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_x_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_v_x_u32mf2_ta (uint32_t src, size_t vl) {
+ return vmv_v_x_u32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> [[MERGE:%.*]], <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vmv_v_v_f32mf2_tu (vfloat32mf2_t merge, vfloat32mf2_t src, size_t vl) {
+ return vmv_v_v_f32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_v_v_f32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32.i64(<vscale x 1 x float> undef, <vscale x 1 x float> [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
+//
+vfloat32mf2_t test_vmv_v_v_f32mf2_ta (vfloat32mf2_t src, size_t vl) {
+ return vmv_v_v_f32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_i32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_s_x_i32mf2_tu (vint32mf2_t merge, int32_t src, size_t vl) {
+ return vmv_s_x_i32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_u32mf2_tu(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> [[MERGE:%.*]], i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_s_x_u32mf2_tu (vuint32mf2_t merge, uint32_t src, size_t vl) {
+ return vmv_s_x_u32mf2_tu(merge, src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_i32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vint32mf2_t test_vmv_s_x_i32mf2_ta (int32_t src, size_t vl) {
+ return vmv_s_x_i32mf2_ta(src, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vmv_s_x_u32mf2_ta(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32.i64(<vscale x 1 x i32> undef, i32 [[SRC:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
+//
+vuint32mf2_t test_vmv_s_x_u32mf2_ta (uint32_t src, size_t vl) {
+ return vmv_s_x_u32mf2_ta(src, vl);
+}
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index fc5f705b7fd48..5d3995b7a1db5 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -56,12 +56,20 @@ struct SemaRecord {
// Suffix of overloaded intrinsic name.
SmallVector<PrototypeDescriptor> OverloadedSuffix;
+ // BitMask for supported policies.
+ uint16_t PolicyBitMask;
+
// Number of field, large than 1 if it's segment load/store.
unsigned NF;
bool HasMasked :1;
bool HasVL :1;
bool HasMaskedOffOperand :1;
+ bool IsPrototypeDefaultTU : 1;
+ bool HasTailPolicy : 1;
+ bool HasMaskPolicy : 1;
+ uint8_t UnMaskedPolicyScheme : 2;
+ uint8_t MaskedPolicyScheme : 2;
};
// Compressed function signature table.
@@ -154,7 +162,14 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
OS << " ID = Intrinsic::riscv_" + RVVI->getIRName() + ";\n";
if (RVVI->getNF() >= 2)
OS << " NF = " + utostr(RVVI->getNF()) + ";\n";
+ // We had initialized DefaultPolicy as TU/TUMU in CodeGen function.
+ if (RVVI->getDefaultPolicy() != Policy::TU &&
+ RVVI->getDefaultPolicy() != Policy::TUMU && !RVVI->hasPassthruOperand() &&
+ !RVVI->hasManualCodegen() && RVVI->hasVL())
+ OS << " DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
+
if (RVVI->hasManualCodegen()) {
+ OS << " DefaultPolicy = " << RVVI->getDefaultPolicyBits() << ";\n";
OS << RVVI->getManualCodegen();
OS << "break;\n";
return;
@@ -175,18 +190,19 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI, raw_ostream &OS) {
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
if (RVVI->hasPolicyOperand())
OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
- " TAIL_UNDISTURBED));\n";
+ " DefaultPolicy));\n";
+ if (RVVI->hasMaskedOffOperand() &&
+ RVVI->getDefaultPolicy() == Policy::TAMA)
+ OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
} else {
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
}
} else {
if (RVVI->hasPolicyOperand())
OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
- "TAIL_UNDISTURBED));\n";
- else if (RVVI->hasPassthruOperand()) {
- OS << " Ops.push_back(llvm::UndefValue::get(ResultType));\n";
- OS << " std::rotate(Ops.rbegin(), Ops.rbegin() + 1, Ops.rend());\n";
- }
+ "DefaultPolicy));\n";
+ else if (RVVI->hasPassthruOperand() && RVVI->getDefaultPolicy() == Policy::TA)
+ OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
}
OS << " IntrinsicTypes = {";
@@ -421,19 +437,22 @@ void RVVEmitter::createCodeGen(raw_ostream &OS) {
// IR name could be empty, use the stable sort preserves the relative order.
llvm::stable_sort(Defs, [](const std::unique_ptr<RVVIntrinsic> &A,
const std::unique_ptr<RVVIntrinsic> &B) {
- return A->getIRName() < B->getIRName();
+ if (A->getIRName() == B->getIRName())
+ return (A->getDefaultPolicy() < B->getDefaultPolicy());
+ return (A->getIRName() < B->getIRName());
});
// Map to keep track of which builtin names have already been emitted.
StringMap<RVVIntrinsic *> BuiltinMap;
- // Print switch body when the ir name or ManualCodegen changes from previous
- // iteration.
+ // Print switch body when the ir name, ManualCodegen or policy changes from
+ // previous iteration.
RVVIntrinsic *PrevDef = Defs.begin()->get();
for (auto &Def : Defs) {
StringRef CurIRName = Def->getIRName();
if (CurIRName != PrevDef->getIRName() ||
- (Def->getManualCodegen() != PrevDef->getManualCodegen())) {
+ (Def->getManualCodegen() != PrevDef->getManualCodegen()) ||
+ (Def->getDefaultPolicy() != PrevDef->getDefaultPolicy())) {
emitCodeGenSwitchBody(PrevDef, OS);
}
PrevDef = Def.get();
@@ -485,8 +504,11 @@ void RVVEmitter::createRVVIntrinsics(
Record *UMPSRecord = R->getValueAsDef("UnMaskedPolicyScheme");
auto UnMaskedPolicyScheme =
static_cast<PolicyScheme>(UMPSRecord->getValueAsInt("Value"));
- bool HasUnMaskedOverloaded = R->getValueAsBit("HasUnMaskedOverloaded");
std::vector<int64_t> Log2LMULList = R->getValueAsListOfInts("Log2LMUL");
+ bool HasTailPolicy = R->getValueAsBit("HasTailPolicy");
+ bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy");
+ bool IsPrototypeDefaultTU = R->getValueAsBit("IsPrototypeDefaultTU");
+ bool SupportOverloading = R->getValueAsBit("SupportOverloading");
bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias");
StringRef ManualCodegen = R->getValueAsString("ManualCodegen");
StringRef MaskedManualCodegen = R->getValueAsString("MaskedManualCodegen");
@@ -498,6 +520,11 @@ void RVVEmitter::createRVVIntrinsics(
StringRef MaskedIRName = R->getValueAsString("MaskedIRName");
unsigned NF = R->getValueAsInt("NF");
+ // If unmasked builtin supports policy, they should be TU or TA.
+ SmallVector<Policy> SupportedUnMaskedPolicies = {Policy::TU, Policy::TA};
+ SmallVector<Policy> SupportedMaskedPolicies =
+ RVVIntrinsic::getSupportedMaskedPolicies(HasTailPolicy, HasMaskPolicy);
+
// Parse prototype and create a list of primitive type with transformers
// (operand) in Prototype. Prototype[0] is output operand.
SmallVector<PrototypeDescriptor> BasicPrototype =
@@ -509,10 +536,12 @@ void RVVEmitter::createRVVIntrinsics(
// Compute Builtin types
auto Prototype = RVVIntrinsic::computeBuiltinTypes(
- BasicPrototype, /*IsMasked=*/false, /*HasMaskedOffOperand=*/false,
- HasVL, NF);
+ BasicPrototype, /*IsMasked=*/false,
+ /*HasMaskedOffOperand=*/false, HasVL, NF, IsPrototypeDefaultTU,
+ UnMaskedPolicyScheme);
auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes(
- BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF);
+ BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF,
+ IsPrototypeDefaultTU, MaskedPolicyScheme);
// Create Intrinsics for each type and LMUL.
for (char I : TypeRange) {
@@ -531,21 +560,54 @@ void RVVEmitter::createRVVIntrinsics(
Out.push_back(std::make_unique<RVVIntrinsic>(
Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
/*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL,
- UnMaskedPolicyScheme, HasUnMaskedOverloaded, HasBuiltinAlias,
- ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF));
- if (HasMasked) {
- // Create a masked intrinsic
- Optional<RVVTypes> MaskTypes =
- RVVType::computeTypes(BT, Log2LMUL, NF, MaskedPrototype);
+ UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
+ ManualCodegen, *Types, IntrinsicTypes, RequiredFeatures, NF,
+ Policy::PolicyNone, IsPrototypeDefaultTU));
+ if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone)
+ for (auto P : SupportedUnMaskedPolicies) {
+ SmallVector<PrototypeDescriptor> PolicyPrototype =
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicPrototype, /*IsMasked=*/false,
+ /*HasMaskedOffOperand=*/false, HasVL, NF,
+ IsPrototypeDefaultTU, UnMaskedPolicyScheme, P);
+ Optional<RVVTypes> PolicyTypes =
+ RVVType::computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
+ Out.push_back(std::make_unique<RVVIntrinsic>(
+ Name, SuffixStr, OverloadedName, OverloadedSuffixStr, IRName,
+ /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL,
+ UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
+ ManualCodegen, PolicyTypes.getValue(), IntrinsicTypes,
+ RequiredFeatures, NF, P, IsPrototypeDefaultTU));
+ }
+ if (!HasMasked)
+ continue;
+ // Create a masked intrinsic
+ Optional<RVVTypes> MaskTypes =
+ RVVType::computeTypes(BT, Log2LMUL, NF, Prototype);
+ Out.push_back(std::make_unique<RVVIntrinsic>(
+ Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName,
+ /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
+ SupportOverloading, HasBuiltinAlias, MaskedManualCodegen,
+ MaskTypes.getValue(), IntrinsicTypes, RequiredFeatures, NF,
+ Policy::PolicyNone, IsPrototypeDefaultTU));
+ if (MaskedPolicyScheme == PolicyScheme::SchemeNone)
+ continue;
+ for (auto P : SupportedMaskedPolicies) {
+ SmallVector<PrototypeDescriptor> PolicyPrototype =
+ RVVIntrinsic::computeBuiltinTypes(
+ BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
+ NF, IsPrototypeDefaultTU, MaskedPolicyScheme, P);
+ Optional<RVVTypes> PolicyTypes =
+ RVVType::computeTypes(BT, Log2LMUL, NF, PolicyPrototype);
Out.push_back(std::make_unique<RVVIntrinsic>(
Name, SuffixStr, OverloadedName, OverloadedSuffixStr,
- MaskedIRName,
- /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme,
- HasUnMaskedOverloaded, HasBuiltinAlias, MaskedManualCodegen,
- *MaskTypes, IntrinsicTypes, RequiredFeatures, NF));
+ MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL,
+ MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias,
+ MaskedManualCodegen, PolicyTypes.getValue(), IntrinsicTypes,
+ RequiredFeatures, NF, P, IsPrototypeDefaultTU));
}
- } // end for Log2LMULList
- } // end for TypeRange
+ } // End for Log2LMULList
+ } // End for TypeRange
// We don't emit vsetvli and vsetvlimax for SemaRecord.
// They are written in riscv_vector.td and will emit those marco define in
@@ -586,6 +648,11 @@ void RVVEmitter::createRVVIntrinsics(
SR.HasMasked = HasMasked;
SR.HasVL = HasVL;
SR.HasMaskedOffOperand = HasMaskedOffOperand;
+ SR.IsPrototypeDefaultTU = IsPrototypeDefaultTU;
+ SR.HasTailPolicy = HasTailPolicy;
+ SR.HasMaskPolicy = HasMaskPolicy;
+ SR.UnMaskedPolicyScheme = static_cast<uint8_t>(UnMaskedPolicyScheme);
+ SR.MaskedPolicyScheme = static_cast<uint8_t>(MaskedPolicyScheme);
SR.Prototype = std::move(BasicPrototype);
SR.Suffix = parsePrototypes(SuffixProto);
SR.OverloadedSuffix = parsePrototypes(OverloadedSuffixProto);
@@ -626,6 +693,11 @@ void RVVEmitter::createRVVIntrinsicRecords(std::vector<RVVIntrinsicRecord> &Out,
R.HasMasked = SR.HasMasked;
R.HasVL = SR.HasVL;
R.HasMaskedOffOperand = SR.HasMaskedOffOperand;
+ R.IsPrototypeDefaultTU = SR.IsPrototypeDefaultTU;
+ R.HasTailPolicy = SR.HasTailPolicy;
+ R.HasMaskPolicy = SR.HasMaskPolicy;
+ R.UnMaskedPolicyScheme = SR.UnMaskedPolicyScheme;
+ R.MaskedPolicyScheme = SR.MaskedPolicyScheme;
assert(R.PrototypeIndex !=
static_cast<uint16_t>(SemaSignatureTable::INVALID_INDEX));
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