[clang] 60e1206 - [clang-format] Handle Verilog attributes

[via cfe-commits]

Author: sstwcw
Date: 2022-07-29T00:38:30Z
New Revision: 60e12068ffeb96aa4e56c8dcff3442e516b27ab6

URL: https://github.com/llvm/llvm-project/commit/60e12068ffeb96aa4e56c8dcff3442e516b27ab6
DIFF: https://github.com/llvm/llvm-project/commit/60e12068ffeb96aa4e56c8dcff3442e516b27ab6.diff

LOG: [clang-format] Handle Verilog attributes

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D128709

Added: 
    

Modified: 
    clang/lib/Format/TokenAnnotator.cpp
    clang/lib/Format/UnwrappedLineParser.cpp
    clang/unittests/Format/FormatTestVerilog.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 67ee194e38ea..d148e4532e91 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -4067,6 +4067,9 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line,
          Keywords.isWordLike(Left))) {
       return false;
     }
+    // Add space in attribute like `(* ASYNC_REG = "TRUE" *)`.
+    if (Left.endsSequence(tok::star, tok::l_paren) && Right.is(tok::identifier))
+      return true;
   }
   if (Left.is(TT_ImplicitStringLiteral))
     return Right.hasWhitespaceBefore();

diff  --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
index 8336c4c727aa..1d79cb1a799b 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -1471,6 +1471,23 @@ void UnwrappedLineParser::parseStructuralElement(
     addUnwrappedLine();
     return;
   }
+
+  if (Style.isVerilog()) {
+    // Skip things that can exist before keywords like 'if' and 'case'.
+    while (true) {
+      if (FormatTok->isOneOf(Keywords.kw_priority, Keywords.kw_unique,
+                             Keywords.kw_unique0)) {
+        nextToken();
+      } else if (FormatTok->is(tok::l_paren) &&
+                 Tokens->peekNextToken()->is(tok::star)) {
+        parseParens();
+      } else {
+        break;
+      }
+    }
+  }
+
+  // Tokens that only make sense at the beginning of a line.
   switch (FormatTok->Tok.getKind()) {
   case tok::kw_asm:
     nextToken();

diff  --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index 28980c39dcf3..92931d3e5e74 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -295,6 +295,12 @@ TEST_F(FormatTestVerilog, Hierarchy) {
 TEST_F(FormatTestVerilog, If) {
   verifyFormat("if (x)\n"
                "  x = x;");
+  verifyFormat("unique if (x)\n"
+               "  x = x;");
+  verifyFormat("unique0 if (x)\n"
+               "  x = x;");
+  verifyFormat("priority if (x)\n"
+               "  x = x;");
   verifyFormat("if (x)\n"
                "  x = x;\n"
                "x = x;");
@@ -357,6 +363,14 @@ TEST_F(FormatTestVerilog, If) {
                "  x = {x};\n"
                "else\n"
                "  {x} = {x};");
+
+  // With attributes.
+  verifyFormat("(* x *) if (x)\n"
+               "  x = x;");
+  verifyFormat("(* x = \"x\" *) if (x)\n"
+               "  x = x;");
+  verifyFormat("(* x, x = \"x\" *) if (x)\n"
+               "  x = x;");
 }
 
 TEST_F(FormatTestVerilog, Operators) {