[PATCH] D130387: [CUDA/SPIR-V] Force passing aggregate type byval

[Artem Belevich via Phabricator via cfe-commits]

tra accepted this revision.
tra added a comment.
This revision is now accepted and ready to land.

LGTM with a couple of nits.



================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10450
+
+    if (isAggregateTypeForABI(Ty)) {
+      return getNaturalAlignIndirect(Ty, /* byval */ true);
----------------
I would add a comment that this is a CUDA-specific behavior with the pointer to the relevant CUDA doc explaining what's going on.


================
Comment at: clang/lib/CodeGen/TargetInfo.cpp:10450
+
+    if (isAggregateTypeForABI(Ty)) {
+      return getNaturalAlignIndirect(Ty, /* byval */ true);
----------------
tra wrote:
> I would add a comment that this is a CUDA-specific behavior with the pointer to the relevant CUDA doc explaining what's going on.
Style nit: LLVM does not use braces for single-statement body. 
https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130387/new/

https://reviews.llvm.org/D130387