[PATCH] D128712: [clang-format] Handle Verilog modules

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.


================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:4040
+void UnwrappedLineParser::parseVerilogSensitivityList() {
+  if (!FormatTok->is(tok::at))
+    return;
----------------
I prefer to make such checks before calling the function.
But others have a different opinion.

No blocker for me.


================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:4072
+                                Keywords.kw_randsequence)) {
+    AddLevels += Style.IndentCaseLabels;
+    nextToken();
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Using `bool`s in integer expressions has caused some trouble in code I've seen. I'd prefer to use it as boolean.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128712/new/

https://reviews.llvm.org/D128712