[PATCH] D128714: [clang-format] Handle Verilog case statements

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.


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Comment at: clang/lib/Format/Format.cpp:1265
   LLVMStyle.IndentAccessModifiers = false;
-  LLVMStyle.IndentCaseLabels = false;
+  LLVMStyle.IndentCaseLabels = LLVMStyle.isVerilog() ? true : false;
   LLVMStyle.IndentCaseBlocks = false;
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You should put that below.


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Comment at: clang/lib/Format/Format.cpp:1349
 
   // Defaults that differ when not C++.
   if (Language == FormatStyle::LK_TableGen)
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Here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128714/new/

https://reviews.llvm.org/D128714