[clang] 0f6f429 - Revert "[RISCV] Add vread_csr and vwrite_csr to riscv_vector.h"
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Mon Jun 13 04:31:49 PDT 2022
Author: wangpc
Date: 2022-06-13T19:31:25+08:00
New Revision: 0f6f4295d10fe8cc9c3933b85dc9a66b840e3eca
URL: https://github.com/llvm/llvm-project/commit/0f6f4295d10fe8cc9c3933b85dc9a66b840e3eca
DIFF: https://github.com/llvm/llvm-project/commit/0f6f4295d10fe8cc9c3933b85dc9a66b840e3eca.diff
LOG: Revert "[RISCV] Add vread_csr and vwrite_csr to riscv_vector.h"
This reverts commit aebe24a856d2f40284d940970d4e159319dbb90f.
`REQUIRES` for RISCV target is needed in tests.
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
Removed:
clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 933a6c11f3359..8a1e0eb742582 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1497,56 +1497,6 @@ multiclass RVVPseudoVNCVTBuiltin<string IR, string MName, string type_range,
}
}
-// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
-let HeaderCode =
-[{
-enum RVV_CSR {
- RVV_VSTART = 0,
- RVV_VXSAT,
- RVV_VXRM,
- RVV_VCSR,
-};
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-unsigned long vread_csr(enum RVV_CSR __csr) {
- unsigned long __rv = 0;
- switch (__csr) {
- case RVV_VSTART:
- __asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
- break;
- case RVV_VXSAT:
- __asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
- break;
- case RVV_VXRM:
- __asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
- break;
- case RVV_VCSR:
- __asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
- break;
- }
- return __rv;
-}
-
-static __inline__ __attribute__((__always_inline__, __nodebug__))
-void vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
- switch (__csr) {
- case RVV_VSTART:
- __asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
- break;
- case RVV_VXSAT:
- __asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
- break;
- case RVV_VXRM:
- __asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
- break;
- case RVV_VCSR:
- __asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
- break;
- }
-}
-}] in
-def vread_vwrite_csr: RVVHeader;
-
// 6. Configuration-Setting Instructions
// 6.1. vsetvli/vsetvl instructions
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
deleted file mode 100644
index 090bc93d20c2b..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck %s
-
-#include <riscv_vector.h>
-
-// CHECK-LABEL: @vread_csr_vstart(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vstart", "=r,~{memory}"() #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT: ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vstart(void) {
- return vread_csr(RVV_VSTART);
-}
-
-// CHECK-LABEL: @vread_csr_vxsat(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxsat", "=r,~{memory}"() #[[ATTR1]], !srcloc !5
-// CHECK-NEXT: ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxsat(void) {
- return vread_csr(RVV_VXSAT);
-}
-
-// CHECK-LABEL: @vread_csr_vxrm(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vxrm", "=r,~{memory}"() #[[ATTR1]], !srcloc !6
-// CHECK-NEXT: ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vxrm(void) {
- return vread_csr(RVV_VXRM);
-}
-
-// CHECK-LABEL: @vread_csr_vcsr(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 asm sideeffect "csrr\09$0, vcsr", "=r,~{memory}"() #[[ATTR1]], !srcloc !7
-// CHECK-NEXT: ret i64 [[TMP0]]
-//
-unsigned long vread_csr_vcsr(void) {
- return vread_csr(RVV_VCSR);
-}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
deleted file mode 100644
index 119fc018595e2..0000000000000
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c
+++ /dev/null
@@ -1,41 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone -emit-llvm %s -o - \
-// RUN: | opt -S -O2 | FileCheck %s
-
-#include <riscv_vector.h>
-
-// CHECK-LABEL: @vwrite_csr_vstart(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void asm sideeffect "csrw\09vstart, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1:[0-9]+]], !srcloc !4
-// CHECK-NEXT: ret void
-//
-void vwrite_csr_vstart(unsigned long value) {
- vwrite_csr(RVV_VSTART, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxsat(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void asm sideeffect "csrw\09vxsat, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !5
-// CHECK-NEXT: ret void
-//
-void vwrite_csr_vxsat(unsigned long value) {
- vwrite_csr(RVV_VXSAT, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vxrm(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void asm sideeffect "csrw\09vxrm, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !6
-// CHECK-NEXT: ret void
-//
-void vwrite_csr_vxrm(unsigned long value) {
- vwrite_csr(RVV_VXRM, value);
-}
-
-// CHECK-LABEL: @vwrite_csr_vcsr(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void asm sideeffect "csrw\09vcsr, ${0:z}", "rJ,~{memory}"(i64 [[VALUE:%.*]]) #[[ATTR1]], !srcloc !7
-// CHECK-NEXT: ret void
-//
-void vwrite_csr_vcsr(unsigned long value) {
- vwrite_csr(RVV_VCSR, value);
-}
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