[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives

[sstwcw via Phabricator via cfe-commits]

sstwcw marked 3 inline comments as done.
sstwcw added inline comments.


================
Comment at: clang/lib/Format/FormatToken.h:1142
+    VerilogExtraKeywords =
+        std::unordered_set<IdentifierInfo *>({kw_always,
+                                              kw_always_comb,
----------------
Now that I added `kw_` to `verilogHashHash`, four columns can't fit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124749/new/

https://reviews.llvm.org/D124749