[PATCH] D123450: [clang-format] Parse Verilog if statements

[sstwcw via Phabricator via cfe-commits]

sstwcw updated this revision to Diff 435777.
sstwcw added a comment.

- add brace


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123450/new/

https://reviews.llvm.org/D123450

Files:
  clang/docs/ClangFormat.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/tools/clang-format/ClangFormat.cpp
  clang/unittests/Format/CMakeLists.txt
  clang/unittests/Format/FormatTestUtils.h
  clang/unittests/Format/FormatTestVerilog.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D123450.435777.patch
Type: text/x-patch
Size: 27367 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/cfe-commits/attachments/20220610/50252d2c/attachment-0001.bin>