[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.


================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1121
+  const char *Start = Lex->getBufferLocation();
+  if (!VerilogToken.match(StringRef(Start, Lex->getBuffer().end() - Start),
+                          &Matches))
----------------
Add braces. Maybe check all other added ifs too. You can check with clang-format with `InsertBraces` and `RemoveBracesLLVM`.


================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:1891
+      // Verilog macro expansions begin with a backtick. For C++ we assume what
+      // looks like one is one.
       TokenCount = Line->Tokens.size();
----------------



================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:1893
       TokenCount = Line->Tokens.size();
-      if (TokenCount == 1 ||
-          (TokenCount == 2 && Line->Tokens.front().Tok->is(tok::comment))) {
-        if (FormatTok->is(tok::colon) && !Line->MustBeDeclaration) {
-          Line->Tokens.begin()->Tok->MustBreakBefore = true;
-          parseLabel(!Style.IndentGotoLabels);
-          if (HasLabel)
-            *HasLabel = true;
-          return;
+      {
+        const UnwrappedLineNode *Tok = &Line->Tokens.front(),
----------------
I find just scopes a bit confusing. Maybe put the check if we want to break into a lambda and call that?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124749/new/

https://reviews.llvm.org/D124749