[PATCH] D126845: [clang-format] Handle Verilog numbers and operators
Owen Pan via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 2 21:55:57 PDT 2022
owenpan added inline comments.
================
Comment at: clang/lib/Format/FormatToken.h:138-139
TYPE(CSharpGenericTypeConstraintComma) \
+ TYPE(VerilogNumberBase) /* for the base in a number literal, not including \
+ the quote */ \
TYPE(Unknown)
----------------
HazardyKnusperkeks wrote:
> One should move the CSharp stuff, since all other languages are sorted correctly. So I'd say please move above the CSharp.
Can you move the comment to above the code?
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Comment at: clang/lib/Format/FormatTokenLexer.cpp:247
+ TT_BinaryOperator))
+ return;
+ // Module paths in specify blocks and implications in properties.
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HazardyKnusperkeks wrote:
> I think here are braces needed.
+1. And other places where the conditional and/or the body can't fit on a single line.
================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1102
FormatTok->Tok.setKind(tok::hashhash);
+ } else if (Tokens.size() != 0 && Tokens.back()->is(Keywords.quote) &&
+ NumberBase.match(FormatTok->TokenText, &Matches)) {
----------------
================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1104
+ NumberBase.match(FormatTok->TokenText, &Matches)) {
+ // In Verilog a in based number literal like `'b10`, there may be
+ // whitespace between `'b` and `10`. Therefore we handle the base and
----------------
================
Comment at: clang/lib/Format/FormatTokenLexer.cpp:1152
+ if (Style.isVerilog() && Tokens.size() != 0 &&
+ Tokens.back()->is(TT_VerilogNumberBase) &&
----------------
================
Comment at: clang/lib/Format/FormatTokenLexer.h:63
+ // Merge the most lately lexed tokens into a single token if their kinds are
+ // correct.
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Merge the most //recently// lexed tokens?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D126845/new/
https://reviews.llvm.org/D126845
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