[PATCH] D124749: [clang-format] Handle Verilog preprocessor directives
sstwcw via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Jun 2 02:40:41 PDT 2022
sstwcw marked 2 inline comments as done.
sstwcw added inline comments.
================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:1889
TokenCount = Line->Tokens.size();
- if (TokenCount == 1 ||
- (TokenCount == 2 && Line->Tokens.front().Tok->is(tok::comment))) {
----------------
HazardyKnusperkeks wrote:
> Why did you remove that if?
Previously the if checked whether the line is comment and an identifier. For Verilog it's comment, a backtick, and an identifier. I found it easier to break if the line doesn't match the pattern.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124749/new/
https://reviews.llvm.org/D124749
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