[PATCH] D125947: [RISCV] Add default ABI for archs with only F extension
Wang Pengcheng via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed May 18 23:18:43 PDT 2022
pcwang-thead created this revision.
pcwang-thead added reviewers: asb, craig.topper, benshi001, luismarques, jrtc27.
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It seems that we use ilp32/lp64 ABI for these archs with
only single-precision floating-point extension. I believe
that users would like to pass arguments by floating-point
registers if they provide F extension in -march. So here
we use ilp32f and lp64f for these cases.
For some existed tests, we set `-target-abi` explicitly
to keep consistent.
@benshi001 has proposed this before and I think it is
necessary.
Links:
- https://reviews.llvm.org/D103878
- https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D125947
Files:
clang/test/CodeGen/RISCV/riscv-metadata.c
clang/test/Driver/riscv-abi.c
clang/test/Driver/riscv-cpus.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
llvm/test/CodeGen/RISCV/calling-conv-half.ll
llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/half-fcmp.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
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