[PATCH] D122377: [PowerPC] Support 16-byte lock free atomics on pwr8 and up

[Hubert Tong via Phabricator via cfe-commits]

hubert.reinterpretcast accepted this revision.
hubert.reinterpretcast added a comment.
This revision is now accepted and ready to land.

LGTM with minor comments.



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Comment at: clang/test/CodeGen/PowerPC/atomic-alignment.c:1-12
 // RUN: %clang_cc1 -verify -triple powerpc-unknown-unknown -emit-llvm -o - %s | \
 // RUN:   FileCheck %s --check-prefixes=PPC,PPC32
 // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - %s | \
 // RUN:   FileCheck %s --check-prefixes=PPC,PPC64
+// RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux -emit-llvm -o - %s \
+// RUN:   -target-cpu pwr8 | FileCheck %s --check-prefixes=PPC,PPC64
 // RUN: %clang_cc1 -verify -triple powerpc64-unknown-aix -emit-llvm -o - %s | \
----------------
Use `-Werror` in place of `-verify` with no diagnostics.


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Comment at: clang/test/CodeGen/PowerPC/quadword-atomics.c:1-6
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64-PWR8
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
+// RUN:   -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
+// RUN: %clang_cc1 -verify -Wno-atomic-alignment -triple powerpc64-unknown-aix \
+// RUN:   -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s --check-prefix=PPC64
----------------
Same comment as for the other file.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:18057
+bool PPCTargetLowering::shouldInlineQuadwordAtomics() const {
+  // TODO: 16-byte atomic type support for AIX is in progress, we should be able
+  // to inline 16-byte atomic ops on AIX too in the future.
----------------
Minor nit: Use semicolon.


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Comment at: llvm/test/CodeGen/PowerPC/atomics-i128.ll:160
+; LE-PWR8-NEXT:    adde r8, r5, r6
+; LE-PWR8-NEXT:    stqcx. r8, 0, r3
+; LE-PWR8-NEXT:    bne cr0, .LBB1_1
----------------
I have verified that the registers in the pairs are used correctly for this case. I've skimmed the other cases for the instructions applied to the loaded value (or, for non-inline cases, the functions called).

I did not check that the set-up for the calls, etc.

I also haven't looked into the memory barrier instruction usage (but that should be common with other widths).


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D122377/new/

https://reviews.llvm.org/D122377