[PATCH] D122732: [Clang][AArch64][SVE] Allow subscript operator for SVE types

[David Truby via Phabricator via cfe-commits]

DavidTruby added a comment.

> Not sure what you mean by this; LLVM supports extractelement on `<vscale x 16 x i1>` vectors.  I guess the fact that it's a "vscale x 16" element vector might not be intuitive?

It's a native operation at the LLVM level but not at the ISA level, unlike the data registers. Code quality would be quite poor if we just allowed it naively so I thought it better to disallow it to not give the impression it's easy/free. I will update the text in the commit message to make this more clear.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122732/new/

https://reviews.llvm.org/D122732