[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:547
+def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit,
+                                                       FeatureStdExtM,
+                                                       FeatureStdExtA,
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The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm.


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https://reviews.llvm.org/D122556