[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

[Fangrui Song via Phabricator via cfe-commits]

MaskRay added inline comments.


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Comment at: clang/test/CodeGen/RISCV/riscv-metadata.c:18
 
+// Test if Xiangshan processors work with -target-cpu
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - -target-cpu xiangshan-yanqihu %s | FileCheck -check-prefix=EMPTY-LP64 %s
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RUN lines in this file are unnecessary. mcpu=sifive-u74 is an arbitrary choice and provides the needed coverage. Don't add more CPUs here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122556/new/

https://reviews.llvm.org/D122556