[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

[Zircon Liu via Phabricator via cfe-commits]

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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122556

Files:
  clang/test/CodeGen/RISCV/riscv-metadata.c
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td

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