[PATCH] D122513: [analyzer] Fix "RhsLoc and LhsLoc bitwidth must be same"

[Artem Dergachev via Phabricator via cfe-commits]

NoQ added a comment.

Why doesn't the AST handle this for us through implicit casts? Do we really need to duplicate type promotion logic in the static analyzer?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D122513/new/

https://reviews.llvm.org/D122513