[PATCH] D121758: [clang-format] Add support for formatting Verilog code

[sstwcw via Phabricator via cfe-commits]

sstwcw added a comment.

Yes.  I am surprised that you asked since everyone asked me to break it apart.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121758/new/

https://reviews.llvm.org/D121758