[PATCH] D121758: [clang-format] Add support for formatting Verilog code

[MyDeveloperDay via Phabricator via cfe-commits]

MyDeveloperDay added a comment.

Firstly thank you for taking the time to submit the patch, I've only taken a cursory view at first and I definitely have some comments, I've added the main clang-format reviewers

This is a very invasive patch so there are a number of things we might want to do to limit its size.

To start you off lets do some housekeeping..

1. Can you please add a release note
2. Can you add the changes to the ClangFormat.rst
3. Can you log a github issue and mention it in the summary
4. This needs a better summary explaining the rational for adding Verilog and what style guide we are following


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121758/new/

https://reviews.llvm.org/D121758