[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

Craig Topper via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Wed Mar 2 15:16:57 PST 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4671
+  if (HasMask) {
+    for (size_t i = 2; i < NumOperands; i++) {
+      Ops.push_back(Op.getOperand(i));
----------------
Drop curly braces


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4675
+  } else {
+    for (size_t i = 2; i < NumOperands - 1; i++) {
+      Ops.push_back(Op.getOperand(i));
----------------
Drop curly braces


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4673
 //===----------------------------------------------------------------------===//
-defm PseudoVFCVT_XU_F : VPseudoVCVTI_V;
-defm PseudoVFCVT_X_F : VPseudoVCVTI_V;
+let mayRaiseFPException = true in {
 defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
----------------
kito-cheng wrote:
> kito-cheng wrote:
> > I saw all other target using `0`/`1` rather than `true`/`false` including `RISCVInstrInfoF.td`/`RISCVInstrInfoD.td`when setting mayRaiseFPException, maybe we should keep it consistent? 
> And I think we should also set `mayRaiseFPException` in `RISCVInstrInfoV.td`.
`true`/`false` are relatively new to tablegen. They were introduced in Nov. 2020. I don't think I've fully adjusted to their existence so I probably put 0/1 in the scalar code out of habit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120449/new/

https://reviews.llvm.org/D120449



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