[PATCH] D112774: [RISCV] Support k-ext clang intrinsics
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 2 14:20:21 PST 2022
craig.topper added inline comments.
Herald added a project: All.
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Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:75
+// Zbkb extension
+TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_zip, "ZiZi", "nc", "zbkb")
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Shouldn't brev8 be using "LiLi"?
================
Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:76
+TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_zip, "ZiZi", "nc", "zbkb")
+TARGET_BUILTIN(__builtin_riscv_unzip, "ZiZi", "nc", "zbkb")
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Please add `_32` to the end of zip and unzip.
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Comment at: clang/lib/Sema/SemaChecking.cpp:4092
+ case RISCV::BI__builtin_riscv_sm4ed:
+ return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
}
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What about aes64ks1i's rnum?
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Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbkb.c:13
+//
+int brev8(int rs1)
+{
----------------
This should be long not int
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Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c:1
+
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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Extra blank line at the top of the file
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Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c:9
+// RV64ZBKB-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBKB-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
+// RV64ZBKB-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
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These should be i64
================
Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbkb.c:14
+//
+int brev8(int rs1)
+{
----------------
This should be `long` not `int`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112774/new/
https://reviews.llvm.org/D112774
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