[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added a comment.

Here's a fix that I tested on the original repreoduce. It detects that we picked one of the new register classes and tries to redirect back to the normal GPR register class if the GPR register class has the same width. I also checked for MVT::Other to use the GPR class if there was no type.

  diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  index 3daf2d03de03..4984872139c5 100644
  --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  @@ -10893,7 +10893,28 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       }
     }
   
  -  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
  +  std::pair<Register, const TargetRegisterClass*> Res;
  +  Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
  +
  +  if (Res.second == &RISCV::GPRF32RegClass) {
  +    if (!Subtarget.is64Bit() || VT == MVT::Other)
  +      return std::make_pair(Res.first, &RISCV::GPRRegClass);
  +    return std::make_pair(0, nullptr);
  +  }
  +
  +  if (Res.second == &RISCV::GPRF64RegClass) {
  +    if (Subtarget.is64Bit() || VT == MVT::Other)
  +      return std::make_pair(Res.first, &RISCV::GPRRegClass);
  +    return std::make_pair(0, nullptr);
  +  }
  +
  +  if (Res.second == &RISCV::GPRF16RegClass) {
  +    if (VT == MVT::Other)
  +      return std::make_pair(Res.first, &RISCV::GPRRegClass);
  +    return std::make_pair(0, nullptr);
  +  }
  +
  +  return Res;
   }


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  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298