[PATCH] D119720: [ARM] Pass for Cortex-A57 and Cortex-A72 Fused AES Erratum

[Dave Green via Phabricator via cfe-commits]

dmgreen added a comment.

I have a high level question regarding RDF, as I've not seen it used in many other places, so it may be under-tested on Arm systems at the moment. This currently, for all code, builds an rdf graph, analyze the rdf graph for a fairly rare instructions, then fixes up the code based on that.  It might be best to avoid the (possibly expensive?) rdf graph generation for the common case where the instructions are not present. Check that the instruction exists first.

It might then be simpler to just search back for the def of a register, considering in most code the instruction we are looking for should be fairly rare and we won't expect to need to find def's in bulk. That might be simpler overall, and avoid some of the difficulties of RDF.



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Comment at: llvm/test/CodeGen/ARM/aes-erratum-fix.ll:49
+
+define <16 x i8> @aese_once_via_val(<16 x i8> %0, <16 x i8> %1) nounwind {
+; CHECK-FIX-NOSCHED-LABEL: aese_once_via_val:
----------------
Adding arm_aapcs_vfpcc will make the function "hardfp", which might be useful for testing inputs from argument that don't need to be passed via gpr regs.


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https://reviews.llvm.org/D119720