[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Nikita Popov via Phabricator via cfe-commits]

nikic added a comment.

Because I happened to also run into this, reduced IR for `-mtriple=riscv32 -mattr=+d` is:

  define float @test(float %x) {
    %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00)
    ret float 0.000000e+00
  }


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298