[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension
Shao-Ce SUN via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Thu Feb 10 05:04:03 PST 2022
achieveartificialintelligence added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+ X10_PD, X12_PD, X14_PD, X16_PD,
> Jim wrote:
> > Is XLenRI correct for GPRPF64? RV32 has size 32.
> I'm not sure the RegInfos are correct for the other classes either. The RegInfos override the register size, the spill size, and spill alignment. I think those should all be based on the FP type.
> So I don't think any of these should have a RegInfos.
Without `RegInfo`, it would cause `spill size` to be changed for a large number of other tests.
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