[PATCH] D117920: [RISCV] Decouple V and Zve64*

[Yueh-Ting Chen via Phabricator via cfe-commits]

eopXD created this revision.
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Now with existing macros to imply elen and elen_fp for rvv, we should decouple
the implication between V and Zve*.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117920

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/utils/TableGen/RISCVVEmitter.cpp
  llvm/lib/Support/RISCVISAInfo.cpp


Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -690,7 +690,7 @@
   bool HasE = Exts.count("e") == 1;
   bool HasD = Exts.count("d") == 1;
   bool HasF = Exts.count("f") == 1;
-  bool HasVector = Exts.count("zve32x") == 1;
+  bool HasVector = Exts.count("v") == 1 || Exts.count("zve32x") == 1;
   bool HasZve32f = Exts.count("zve32f") == 1;
   bool HasZve64d = Exts.count("zve64d") == 1;
   bool HasZvl = MinVLen != 0;
@@ -732,7 +732,7 @@
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"};
+static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
 static const char *ImpliedExtsZve64d[] = {"zve64f"};
 static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
@@ -844,6 +844,9 @@
   // handles EEW restriction by sub-extension zve
   for (auto Ext : Exts) {
     StringRef ExtName = Ext.first;
+    if (ExtName == "v") {
+      MaxELen = MaxELenFp = 64;
+    }
     bool IsZveExt = ExtName.consume_front("zve");
     if (IsZveExt) {
       if (ExtName.back() == 'f')
Index: clang/utils/TableGen/RISCVVEmitter.cpp
===================================================================
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1034,7 +1034,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-        "ATTRS, \"experimental-zve32x\")\n";
+        "ATTRS, \"experimental-zve32x|v\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
     auto P =
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,7 @@
   if (ISAInfo->hasExtension("c"))
     Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
     Builder.defineMacro("__riscv_vector");
 }
 


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