[clang] 7a275dc - [RISCV] Remove Zvlsseg extension.
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Thu Jan 20 12:40:20 PST 2022
Author: Craig Topper
Date: 2022-01-20T12:40:07-08:00
New Revision: 7a275dc35411b8c3f510166f40c225cd10dc5eec
URL: https://github.com/llvm/llvm-project/commit/7a275dc35411b8c3f510166f40c225cd10dc5eec
DIFF: https://github.com/llvm/llvm-project/commit/7a275dc35411b8c3f510166f40c225cd10dc5eec.diff
LOG: [RISCV] Remove Zvlsseg extension.
This string no longer appears in the Vector Extension specification.
The segment load/store instructions are just part of the vector
instruction set.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D117724
Added:
Modified:
clang/include/clang/Basic/RISCVVTypes.def
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch-invalid.s
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rvv/zvlsseg.s
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/RISCVVTypes.def b/clang/include/clang/Basic/RISCVVTypes.def
index f6ef62a646363..1d4024dfb20d3 100644
--- a/clang/include/clang/Basic/RISCVVTypes.def
+++ b/clang/include/clang/Basic/RISCVVTypes.def
@@ -30,8 +30,8 @@
//
// - ElBits is the size of one element in bits (SEW).
//
-// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions
-// (TODO).
+// - NF is the number of fields (NFIELDS) used in the Load/Store Segment
+// instructions (TODO).
//
// - IsSigned is true for vectors of signed integer elements and
// for vectors of floating-point elements.
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 03e16be96abee..28c57cc6afeeb 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -215,10 +215,10 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
// an automatic definition in header is emitted.
string HeaderCode = "";
- // Sub extension of vector spec. Currently only support Zvlsseg.
+ // Sub extension of vector spec.
list<string> RequiredExtensions = [];
- // Number of fields for Zvlsseg.
+ // Number of fields for Load/Store Segment instructions.
int NF = 1;
}
@@ -1567,7 +1567,6 @@ defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
// 7.8 Vector Load/Store Segment Instructions
-let RequiredExtensions = ["Zvlsseg"] in {
defm : RVVUnitStridedSegLoad<"vlseg">;
defm : RVVUnitStridedSegLoadFF<"vlseg">;
defm : RVVStridedSegLoad<"vlsseg">;
@@ -1577,7 +1576,6 @@ defm : RVVUnitStridedSegStore<"vsseg">;
defm : RVVStridedSegStore<"vssseg">;
defm : RVVIndexedSegStore<"vsuxseg">;
defm : RVVIndexedSegStore<"vsoxseg">;
-}
// 12. Vector Integer Arithmetic Instructions
// 12.1. Vector Single-Width Integer Add and Subtract
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
index 9cb3325218561..0df229dc803da 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
index a0f04dc4375b4..ac49608830570 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
@@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
index f2b9e445b605a..22df2b948634b 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
@@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
index 82c4c57982acb..4f79022bcfd92 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
index a2dbaaf48084f..8db5e8039cafe 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
index 5f41c6bcd28ec..d3454be64ca57 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
index 662ee6b7dbaed..b72721984afa8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
index 8952c2d02ba03..2a95d46f3ae92 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
index f6bfd7844f5a0..3a338ad821e27 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
index 41f4f6997dffc..f278bb76ae630 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
index 11cd459f552ff..deaaf0ed5ff93 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
@@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
index 20a79659f72dc..fba2c179a4446 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
@@ -2,12 +2,12 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -target-feature +zfh \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone \
+// RUN: -disable-O0-optnone \
// RUN: -fallow-half-arguments-and-returns -emit-llvm %s -o - \
// RUN: | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
index 5584d841789dc..cfdf8275483f8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
index bd499de5a1683..b83ff9833e7b9 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
index 03b8667883d71..ac8c4a412e7d0 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
index 6f3927c22ae01..0829100f58ca4 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
index 488a93c5f3a52..b91c023aeede7 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
index aa559161eade1..a6bdc1ad883f3 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
@@ -2,7 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zfh -target-feature +experimental-v \
-// RUN: -target-feature +experimental-zvlsseg -disable-O0-optnone -emit-llvm %s \
+// RUN: -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c81a87c8182ef..656abde4f75e4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -416,25 +416,6 @@
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-V-GOODVERS %s
// RV32-EXPERIMENTAL-V-GOODVERS: "-target-feature" "+experimental-v"
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG %s
-// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: error: invalid arch name 'rv32iv0p10_zvlsseg'
-// RV32-EXPERIMENTAL-ZVLSSEG-NOFLAG: requires '-menable-experimental-extensions'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg -menable-experimental-extensions -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-NOVERS %s
-// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: error: invalid arch name 'rv32iv0p10_zvlsseg'
-// RV32-EXPERIMENTAL-ZVLSSEG-NOVERS: experimental extension requires explicit version number
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
-// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32iv0p10_zvlsseg0p1'
-// RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'
-
-// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
-// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
-// RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"
-
// RUN: %clang -target riscv32-unknown-elf -march=rv32iv0p10_zvl32b0p10 -### %s -c 2>&1 | \
// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32iv0p10_zvl32b0p10'
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index ba310229f14e5..c69285f6e3996 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -31,7 +31,6 @@
// CHECK-NOT: __riscv_zfh
// CHECK-NOT: __riscv_v
// CHECK-NOT: __riscv_vector
-// CHECK-NOT: __riscv_zvlsseg
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -220,7 +219,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s
// CHECK-V-EXT: __riscv_v 10000{{$}}
// CHECK-V-EXT: __riscv_vector 1
-// CHECK-V-EXT: __riscv_zvlsseg 10000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
index d3f1d63185f4a..84da6a5901a43 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -140,8 +140,7 @@ enum RISCVExtension : uint8_t {
F = 1 << 1,
D = 1 << 2,
Zfh = 1 << 3,
- Zvlsseg = 1 << 4,
- RV64 = 1 << 5,
+ RV64 = 1 << 4,
};
// TODO refactor RVVIntrinsic class design after support all intrinsic
@@ -445,8 +444,8 @@ void RVVType::initBuiltinStr() {
return;
}
BuiltinStr = "q" + utostr(Scale.getValue()) + BuiltinStr;
- // Pointer to vector types. Defined for Zvlsseg load intrinsics.
- // Zvlsseg load intrinsics have pointer type arguments to store the loaded
+ // Pointer to vector types. Defined for segment load intrinsics.
+ // segment load intrinsics have pointer type arguments to store the loaded
// vector values.
if (IsPointer)
BuiltinStr += "*";
@@ -797,8 +796,6 @@ RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix,
RISCVExtensions |= RISCVExtension::D;
}
for (auto Extension : RequiredExtensions) {
- if (Extension == "Zvlsseg")
- RISCVExtensions |= RISCVExtension::Zvlsseg;
if (Extension == "RV64")
RISCVExtensions |= RISCVExtension::RV64;
}
@@ -1311,8 +1308,6 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
OS << LS << "defined(__riscv_d)";
if (Extents & RISCVExtension::Zfh)
OS << LS << "defined(__riscv_zfh)";
- if (Extents & RISCVExtension::Zvlsseg)
- OS << LS << "defined(__riscv_zvlsseg)";
if (Extents & RISCVExtension::RV64)
OS << LS << "(__riscv_xlen == 64)";
OS << "\n";
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index d1d222d3c0eb0..fc52fc6803439 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -66,7 +66,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zbr", RISCVExtensionVersion{0, 93}},
{"zbt", RISCVExtensionVersion{0, 93}},
- {"zvlsseg", RISCVExtensionVersion{0, 10}},
{"zvl32b", RISCVExtensionVersion{0, 10}},
{"zvl64b", RISCVExtensionVersion{0, 10}},
{"zvl128b", RISCVExtensionVersion{0, 10}},
@@ -301,9 +300,7 @@ void RISCVISAInfo::toFeatures(
if (ExtName == "i")
continue;
- if (ExtName == "zvlsseg") {
- Features.push_back("+experimental-zvlsseg");
- } else if (isExperimentalExtension(ExtName)) {
+ if (isExperimentalExtension(ExtName)) {
Features.push_back(StrAlloc("+experimental-" + ExtName));
} else {
Features.push_back(StrAlloc("+" + ExtName));
@@ -691,7 +688,6 @@ Error RISCVISAInfo::checkDependency() {
bool HasE = Exts.count("e") == 1;
bool HasD = Exts.count("d") == 1;
bool HasF = Exts.count("f") == 1;
- bool HasZvlsseg = Exts.count("zvlsseg") == 1;
bool HasVector = Exts.count("zve32x") == 1;
bool HasZve32f = Exts.count("zve32f") == 1;
bool HasZve64d = Exts.count("zve64d") == 1;
@@ -710,11 +706,6 @@ Error RISCVISAInfo::checkDependency() {
return createStringError(errc::invalid_argument,
"d requires f extension to also be specified");
- if (HasZvlsseg && !HasVector)
- return createStringError(
- errc::invalid_argument,
- "zvlsseg requires v or zve* extension to also be specified");
-
// FIXME: Consider Zfinx in the future
if (HasZve32f && !HasF)
return createStringError(
@@ -745,7 +736,7 @@ static const char *ImpliedExtsZve64d[] = {"zve64f"};
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
static const char *ImpliedExtsZve32f[] = {"zve32x"};
-static const char *ImpliedExtsZve32x[] = {"zvlsseg", "zvl32b"};
+static const char *ImpliedExtsZve32x[] = {"zvl32b"};
static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index fda400e490a02..36c7263235ab5 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -161,19 +161,11 @@ foreach i = { 6-15 } in {
[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}
-def FeatureStdExtZvlsseg
- : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
- "'Zvlsseg' (Vector segment load/store instructions)",
- []>;
-def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
- AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
- "'Zvlsseg' (Vector segment load/store instructions)">;
-
def FeatureStdExtZve32x
: SubtargetFeature<"experimental-zve32x", "HasStdExtZve32x", "true",
"'Zve32x' (Vector Extensions for Embedded Processors "
"with maximal 32 EEW)",
- [FeatureStdExtZvlsseg, FeatureStdExtZvl32b]>;
+ [FeatureStdExtZvl32b]>;
def HasStdExtZve32x : Predicate<"SubTarget->hasStdExtZve32x()">,
AssemblerPredicate<(all_of FeatureStdExtZve32x),
"'Zve32x' (Vector Extensions for Embedded Processors "
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index afdd7c4e8b3a8..306024a3e4fd4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1461,7 +1461,7 @@ foreach n = [2, 4, 8] in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVInstructions]
-let Predicates = [HasStdExtZvlsseg] in {
+let Predicates = [HasVInstructions] in {
foreach nf=2-8 in {
foreach eew = [8, 16, 32] in {
defvar w = !cast<RISCVWidth>("LSWidth"#eew);
@@ -1494,9 +1494,9 @@ let Predicates = [HasStdExtZvlsseg] in {
"vsoxseg"#nf#"ei"#eew#".v">;
}
}
-} // Predicates = [HasStdExtZvlsseg]
+} // Predicates = [HasVInstructions]
-let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in {
+let Predicates = [HasVInstructionsI64] in {
foreach nf=2-8 in {
// Vector Unit-strided Segment Instructions
def VLSEG#nf#E64_V :
@@ -1512,8 +1512,8 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64] in {
def VSSSEG#nf#E64_V :
VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
}
-} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64]
-let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in {
+} // Predicates = [HasVInstructionsI64]
+let Predicates = [HasVInstructionsI64, IsRV64] in {
foreach nf=2-8 in {
// Vector Indexed Segment Instructions
def VLUXSEG#nf#EI64_V :
@@ -1529,6 +1529,6 @@ let Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64] in {
VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64,
"vsoxseg"#nf#"ei64.v">;
}
-} // Predicates = [HasStdExtZvlsseg, HasVInstructionsI64, IsRV64]
+} // Predicates = [HasVInstructionsI64, IsRV64]
include "RISCVInstrInfoVPseudos.td"
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 2d80d9d670403..4655015a9d1ec 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -17,7 +17,7 @@ def RocketModel : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = false;
- let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64, HasStdExtZvlsseg];
+ let UnsupportedFeatures = [HasStdExtV, HasVInstructions, HasVInstructionsI64];
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index b39082f153543..3b3e2699d6b60 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -15,7 +15,7 @@ def SiFive7Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 0;
- let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
+ let UnsupportedFeatures = [HasStdExtV];
}
// The SiFive7 microarchitecture has two pipelines: A and B.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index f8eb8e000a6a3..d55affd0539be 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -81,7 +81,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZve64x = false;
bool HasStdExtZve64f = false;
bool HasStdExtZve64d = false;
- bool HasStdExtZvlsseg = false;
bool HasStdExtZfhmin = false;
bool HasStdExtZfh = false;
bool HasRV64 = false;
@@ -160,7 +159,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZve64x() const { return HasStdExtZve64x; }
bool hasStdExtZve64f() const { return HasStdExtZve64f; }
bool hasStdExtZve64d() const { return HasStdExtZve64d; }
- bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index f04eb26282ca5..59790c9967111 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -18,7 +18,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV32V %s
-; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -37,7 +37,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - | FileCheck --check-prefix=RV64V %s
-; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+experimental-v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
@@ -57,8 +57,8 @@
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -77,8 +77,8 @@
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v0p10_zfh1p0_zfhmin1p0_zbb1p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch-invalid.s b/llvm/test/MC/RISCV/attribute-arch-invalid.s
index 933de2963dbbc..1dd5621d128ba 100644
--- a/llvm/test/MC/RISCV/attribute-arch-invalid.s
+++ b/llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -26,5 +26,5 @@
.attribute arch, "rv32izbt"
# CHECK: error: invalid arch name 'rv32izbt', experimental extension requires explicit version number `zbt`
-.attribute arch, "rv32ivzvlsseg"
-# CHECK: error: invalid arch name 'rv32ivzvlsseg', experimental extension requires explicit version number `v`
+.attribute arch, "rv32iv"
+# CHECK: error: invalid arch name 'rv32iv', experimental extension requires explicit version number `v`
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 54e496c61f4ad..3d7be42caeb56 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -36,7 +36,7 @@
## Experimental extensions require version string to be explicitly specified
.attribute arch, "rv32iv0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32izba1p0"
# CHECK: attribute 5, "rv32i2p0_zba1p0"
@@ -74,56 +74,56 @@
.attribute arch, "rv32ifzfh1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh1p0_zfhmin1p0"
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+.attribute arch, "rv32iv0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl32b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl64b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl128b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl256b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl512b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl1024b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl2048b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl4096b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10"
.attribute arch, "rv32iv0p10zvl8192b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl16384b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl32768b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10"
.attribute arch, "rv32iv0p10zvl65536b0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_v0p10_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10"
.attribute arch, "rv32i_zve32x0p10"
-# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32if_zve32f0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zvl32b0p10"
.attribute arch, "rv32i_zve64x0p10"
-# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_zve32x0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32if_zve64f0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_zve32f0p10_zve32x0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
.attribute arch, "rv32ifd_zve64d0p10"
-# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+# CHECK: attribute 5, "rv32i2p0_f2p0_d2p0_zve32f0p10_zve32x0p10_zve64d0p10_zve64f0p10_zve64x0p10_zvl32b0p10_zvl64b0p10"
diff --git a/llvm/test/MC/RISCV/rvv/zvlsseg.s b/llvm/test/MC/RISCV/rvv/zvlsseg.s
index 99f5e157131fe..6845839fcaa33 100644
--- a/llvm/test/MC/RISCV/rvv/zvlsseg.s
+++ b/llvm/test/MC/RISCV/rvv/zvlsseg.s
@@ -1,3036 +1,3034 @@
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
-# RUN: --mattr=+experimental-zvlsseg --riscv-no-aliases \
+# RUN: --riscv-no-aliases \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
-# RUN: --mattr=+experimental-zvlsseg %s \
-# RUN: | llvm-objdump -d --mattr=+experimental-v --mattr=+experimental-zvlsseg -M no-aliases - \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v -M no-aliases - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v \
-# RUN: --mattr=+experimental-zvlsseg %s \
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vlseg2e8.v v8, (a0), v0.t
# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 20 <unknown>
vlseg2e8.v v8, (a0)
# CHECK-INST: vlseg2e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 22 <unknown>
vlseg2e16.v v8, (a0), v0.t
# CHECK-INST: vlseg2e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 20 <unknown>
vlseg2e16.v v8, (a0)
# CHECK-INST: vlseg2e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 22 <unknown>
vlseg2e32.v v8, (a0), v0.t
# CHECK-INST: vlseg2e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 20 <unknown>
vlseg2e32.v v8, (a0)
# CHECK-INST: vlseg2e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 22 <unknown>
vlseg2e64.v v8, (a0), v0.t
# CHECK-INST: vlseg2e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 20 <unknown>
vlseg2e64.v v8, (a0)
# CHECK-INST: vlseg2e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 22 <unknown>
vlseg2e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 21 <unknown>
vlseg2e8ff.v v8, (a0)
# CHECK-INST: vlseg2e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 23 <unknown>
vlseg2e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 21 <unknown>
vlseg2e16ff.v v8, (a0)
# CHECK-INST: vlseg2e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 23 <unknown>
vlseg2e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 21 <unknown>
vlseg2e32ff.v v8, (a0)
# CHECK-INST: vlseg2e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 23 <unknown>
vlseg2e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 21 <unknown>
vlseg2e64ff.v v8, (a0)
# CHECK-INST: vlseg2e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 23 <unknown>
vlsseg2e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
vlsseg2e8.v v8, (a0), a1
# CHECK-INST: vlsseg2e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
vlsseg2e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
vlsseg2e16.v v8, (a0), a1
# CHECK-INST: vlsseg2e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
vlsseg2e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
vlsseg2e32.v v8, (a0), a1
# CHECK-INST: vlsseg2e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
vlsseg2e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
vlsseg2e64.v v8, (a0), a1
# CHECK-INST: vlsseg2e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
vluxseg2ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 24 <unknown>
vluxseg2ei8.v v8, (a0), v4
# CHECK-INST: vluxseg2ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 26 <unknown>
vluxseg2ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 24 <unknown>
vluxseg2ei16.v v8, (a0), v4
# CHECK-INST: vluxseg2ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 26 <unknown>
vluxseg2ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 24 <unknown>
vluxseg2ei32.v v8, (a0), v4
# CHECK-INST: vluxseg2ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 26 <unknown>
vluxseg2ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 24 <unknown>
vluxseg2ei64.v v8, (a0), v4
# CHECK-INST: vluxseg2ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 26 <unknown>
vloxseg2ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 2c <unknown>
vloxseg2ei8.v v8, (a0), v4
# CHECK-INST: vloxseg2ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 2e <unknown>
vloxseg2ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 2c <unknown>
vloxseg2ei16.v v8, (a0), v4
# CHECK-INST: vloxseg2ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 2e <unknown>
vloxseg2ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 2c <unknown>
vloxseg2ei32.v v8, (a0), v4
# CHECK-INST: vloxseg2ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 2e <unknown>
vloxseg2ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 2c <unknown>
vloxseg2ei64.v v8, (a0), v4
# CHECK-INST: vloxseg2ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 2e <unknown>
vlseg3e8.v v8, (a0), v0.t
# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 40 <unknown>
vlseg3e8.v v8, (a0)
# CHECK-INST: vlseg3e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 42 <unknown>
vlseg3e16.v v8, (a0), v0.t
# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 40 <unknown>
vlseg3e16.v v8, (a0)
# CHECK-INST: vlseg3e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 42 <unknown>
vlseg3e32.v v8, (a0), v0.t
# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 40 <unknown>
vlseg3e32.v v8, (a0)
# CHECK-INST: vlseg3e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 42 <unknown>
vlseg3e64.v v8, (a0), v0.t
# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 40 <unknown>
vlseg3e64.v v8, (a0)
# CHECK-INST: vlseg3e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 42 <unknown>
vlseg3e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 41 <unknown>
vlseg3e8ff.v v8, (a0)
# CHECK-INST: vlseg3e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 43 <unknown>
vlseg3e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 41 <unknown>
vlseg3e16ff.v v8, (a0)
# CHECK-INST: vlseg3e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 43 <unknown>
vlseg3e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 41 <unknown>
vlseg3e32ff.v v8, (a0)
# CHECK-INST: vlseg3e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 43 <unknown>
vlseg3e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 41 <unknown>
vlseg3e64ff.v v8, (a0)
# CHECK-INST: vlseg3e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 43 <unknown>
vlsseg3e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
vlsseg3e8.v v8, (a0), a1
# CHECK-INST: vlsseg3e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 4a <unknown>
vlsseg3e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
vlsseg3e16.v v8, (a0), a1
# CHECK-INST: vlsseg3e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 4a <unknown>
vlsseg3e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
vlsseg3e32.v v8, (a0), a1
# CHECK-INST: vlsseg3e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 4a <unknown>
vlsseg3e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
vlsseg3e64.v v8, (a0), a1
# CHECK-INST: vlsseg3e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 4a <unknown>
vluxseg3ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 44 <unknown>
vluxseg3ei8.v v8, (a0), v4
# CHECK-INST: vluxseg3ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 46 <unknown>
vluxseg3ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 44 <unknown>
vluxseg3ei16.v v8, (a0), v4
# CHECK-INST: vluxseg3ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 46 <unknown>
vluxseg3ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 44 <unknown>
vluxseg3ei32.v v8, (a0), v4
# CHECK-INST: vluxseg3ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 46 <unknown>
vluxseg3ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 44 <unknown>
vluxseg3ei64.v v8, (a0), v4
# CHECK-INST: vluxseg3ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 46 <unknown>
vloxseg3ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 4c <unknown>
vloxseg3ei8.v v8, (a0), v4
# CHECK-INST: vloxseg3ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 4e <unknown>
vloxseg3ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 4c <unknown>
vloxseg3ei16.v v8, (a0), v4
# CHECK-INST: vloxseg3ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 4e <unknown>
vloxseg3ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 4c <unknown>
vloxseg3ei32.v v8, (a0), v4
# CHECK-INST: vloxseg3ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 4e <unknown>
vloxseg3ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 4c <unknown>
vloxseg3ei64.v v8, (a0), v4
# CHECK-INST: vloxseg3ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 4e <unknown>
vlseg4e8.v v8, (a0), v0.t
# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 60 <unknown>
vlseg4e8.v v8, (a0)
# CHECK-INST: vlseg4e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 62 <unknown>
vlseg4e16.v v8, (a0), v0.t
# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 60 <unknown>
vlseg4e16.v v8, (a0)
# CHECK-INST: vlseg4e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 62 <unknown>
vlseg4e32.v v8, (a0), v0.t
# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 60 <unknown>
vlseg4e32.v v8, (a0)
# CHECK-INST: vlseg4e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 62 <unknown>
vlseg4e64.v v8, (a0), v0.t
# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 60 <unknown>
vlseg4e64.v v8, (a0)
# CHECK-INST: vlseg4e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 62 <unknown>
vlseg4e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 61 <unknown>
vlseg4e8ff.v v8, (a0)
# CHECK-INST: vlseg4e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 63 <unknown>
vlseg4e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 61 <unknown>
vlseg4e16ff.v v8, (a0)
# CHECK-INST: vlseg4e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 63 <unknown>
vlseg4e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 61 <unknown>
vlseg4e32ff.v v8, (a0)
# CHECK-INST: vlseg4e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 63 <unknown>
vlseg4e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 61 <unknown>
vlseg4e64ff.v v8, (a0)
# CHECK-INST: vlseg4e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 63 <unknown>
vlsseg4e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
vlsseg4e8.v v8, (a0), a1
# CHECK-INST: vlsseg4e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 6a <unknown>
vlsseg4e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
vlsseg4e16.v v8, (a0), a1
# CHECK-INST: vlsseg4e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 6a <unknown>
vlsseg4e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
vlsseg4e32.v v8, (a0), a1
# CHECK-INST: vlsseg4e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 6a <unknown>
vlsseg4e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
vlsseg4e64.v v8, (a0), a1
# CHECK-INST: vlsseg4e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 6a <unknown>
vluxseg4ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 64 <unknown>
vluxseg4ei8.v v8, (a0), v4
# CHECK-INST: vluxseg4ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 66 <unknown>
vluxseg4ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 64 <unknown>
vluxseg4ei16.v v8, (a0), v4
# CHECK-INST: vluxseg4ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 66 <unknown>
vluxseg4ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 64 <unknown>
vluxseg4ei32.v v8, (a0), v4
# CHECK-INST: vluxseg4ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 66 <unknown>
vluxseg4ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 64 <unknown>
vluxseg4ei64.v v8, (a0), v4
# CHECK-INST: vluxseg4ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 66 <unknown>
vloxseg4ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 6c <unknown>
vloxseg4ei8.v v8, (a0), v4
# CHECK-INST: vloxseg4ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 6e <unknown>
vloxseg4ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 6c <unknown>
vloxseg4ei16.v v8, (a0), v4
# CHECK-INST: vloxseg4ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 6e <unknown>
vloxseg4ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 6c <unknown>
vloxseg4ei32.v v8, (a0), v4
# CHECK-INST: vloxseg4ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 6e <unknown>
vloxseg4ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 6c <unknown>
vloxseg4ei64.v v8, (a0), v4
# CHECK-INST: vloxseg4ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 6e <unknown>
vlseg5e8.v v8, (a0), v0.t
# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 80 <unknown>
vlseg5e8.v v8, (a0)
# CHECK-INST: vlseg5e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 82 <unknown>
vlseg5e16.v v8, (a0), v0.t
# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 80 <unknown>
vlseg5e16.v v8, (a0)
# CHECK-INST: vlseg5e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 82 <unknown>
vlseg5e32.v v8, (a0), v0.t
# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 80 <unknown>
vlseg5e32.v v8, (a0)
# CHECK-INST: vlseg5e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 82 <unknown>
vlseg5e64.v v8, (a0), v0.t
# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 80 <unknown>
vlseg5e64.v v8, (a0)
# CHECK-INST: vlseg5e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 82 <unknown>
vlseg5e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 81 <unknown>
vlseg5e8ff.v v8, (a0)
# CHECK-INST: vlseg5e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 83 <unknown>
vlseg5e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 81 <unknown>
vlseg5e16ff.v v8, (a0)
# CHECK-INST: vlseg5e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 83 <unknown>
vlseg5e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 81 <unknown>
vlseg5e32ff.v v8, (a0)
# CHECK-INST: vlseg5e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 83 <unknown>
vlseg5e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 81 <unknown>
vlseg5e64ff.v v8, (a0)
# CHECK-INST: vlseg5e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 83 <unknown>
vlsseg5e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
vlsseg5e8.v v8, (a0), a1
# CHECK-INST: vlsseg5e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
vlsseg5e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
vlsseg5e16.v v8, (a0), a1
# CHECK-INST: vlsseg5e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
vlsseg5e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
vlsseg5e32.v v8, (a0), a1
# CHECK-INST: vlsseg5e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
vlsseg5e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
vlsseg5e64.v v8, (a0), a1
# CHECK-INST: vlsseg5e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
vluxseg5ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 84 <unknown>
vluxseg5ei8.v v8, (a0), v4
# CHECK-INST: vluxseg5ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 86 <unknown>
vluxseg5ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 84 <unknown>
vluxseg5ei16.v v8, (a0), v4
# CHECK-INST: vluxseg5ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 86 <unknown>
vluxseg5ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 84 <unknown>
vluxseg5ei32.v v8, (a0), v4
# CHECK-INST: vluxseg5ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 86 <unknown>
vluxseg5ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 84 <unknown>
vluxseg5ei64.v v8, (a0), v4
# CHECK-INST: vluxseg5ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 86 <unknown>
vloxseg5ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 8c <unknown>
vloxseg5ei8.v v8, (a0), v4
# CHECK-INST: vloxseg5ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 8e <unknown>
vloxseg5ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 8c <unknown>
vloxseg5ei16.v v8, (a0), v4
# CHECK-INST: vloxseg5ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 8e <unknown>
vloxseg5ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 8c <unknown>
vloxseg5ei32.v v8, (a0), v4
# CHECK-INST: vloxseg5ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 8e <unknown>
vloxseg5ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 8c <unknown>
vloxseg5ei64.v v8, (a0), v4
# CHECK-INST: vloxseg5ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 8e <unknown>
vlseg6e8.v v8, (a0), v0.t
# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
vlseg6e8.v v8, (a0)
# CHECK-INST: vlseg6e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
vlseg6e16.v v8, (a0), v0.t
# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
vlseg6e16.v v8, (a0)
# CHECK-INST: vlseg6e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
vlseg6e32.v v8, (a0), v0.t
# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
vlseg6e32.v v8, (a0)
# CHECK-INST: vlseg6e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
vlseg6e64.v v8, (a0), v0.t
# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
vlseg6e64.v v8, (a0)
# CHECK-INST: vlseg6e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
vlseg6e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
vlseg6e8ff.v v8, (a0)
# CHECK-INST: vlseg6e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 a3 <unknown>
vlseg6e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
vlseg6e16ff.v v8, (a0)
# CHECK-INST: vlseg6e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 a3 <unknown>
vlseg6e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
vlseg6e32ff.v v8, (a0)
# CHECK-INST: vlseg6e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 a3 <unknown>
vlseg6e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
vlseg6e64ff.v v8, (a0)
# CHECK-INST: vlseg6e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 a3 <unknown>
vlsseg6e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
vlsseg6e8.v v8, (a0), a1
# CHECK-INST: vlsseg6e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
vlsseg6e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
vlsseg6e16.v v8, (a0), a1
# CHECK-INST: vlsseg6e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
vlsseg6e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
vlsseg6e32.v v8, (a0), a1
# CHECK-INST: vlsseg6e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
vlsseg6e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
vlsseg6e64.v v8, (a0), a1
# CHECK-INST: vlsseg6e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
vluxseg6ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 a4 <unknown>
vluxseg6ei8.v v8, (a0), v4
# CHECK-INST: vluxseg6ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 a6 <unknown>
vluxseg6ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 a4 <unknown>
vluxseg6ei16.v v8, (a0), v4
# CHECK-INST: vluxseg6ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 a6 <unknown>
vluxseg6ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 a4 <unknown>
vluxseg6ei32.v v8, (a0), v4
# CHECK-INST: vluxseg6ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 a6 <unknown>
vluxseg6ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 a4 <unknown>
vluxseg6ei64.v v8, (a0), v4
# CHECK-INST: vluxseg6ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 a6 <unknown>
vloxseg6ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 ac <unknown>
vloxseg6ei8.v v8, (a0), v4
# CHECK-INST: vloxseg6ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 ae <unknown>
vloxseg6ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 ac <unknown>
vloxseg6ei16.v v8, (a0), v4
# CHECK-INST: vloxseg6ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 ae <unknown>
vloxseg6ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 ac <unknown>
vloxseg6ei32.v v8, (a0), v4
# CHECK-INST: vloxseg6ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 ae <unknown>
vloxseg6ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 ac <unknown>
vloxseg6ei64.v v8, (a0), v4
# CHECK-INST: vloxseg6ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 ae <unknown>
vlseg7e8.v v8, (a0), v0.t
# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
vlseg7e8.v v8, (a0)
# CHECK-INST: vlseg7e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
vlseg7e16.v v8, (a0), v0.t
# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
vlseg7e16.v v8, (a0)
# CHECK-INST: vlseg7e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
vlseg7e32.v v8, (a0), v0.t
# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
vlseg7e32.v v8, (a0)
# CHECK-INST: vlseg7e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
vlseg7e64.v v8, (a0), v0.t
# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
vlseg7e64.v v8, (a0)
# CHECK-INST: vlseg7e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
vlseg7e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 c1 <unknown>
vlseg7e8ff.v v8, (a0)
# CHECK-INST: vlseg7e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
vlseg7e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 c1 <unknown>
vlseg7e16ff.v v8, (a0)
# CHECK-INST: vlseg7e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
vlseg7e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 c1 <unknown>
vlseg7e32ff.v v8, (a0)
# CHECK-INST: vlseg7e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
vlseg7e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 c1 <unknown>
vlseg7e64ff.v v8, (a0)
# CHECK-INST: vlseg7e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
vlsseg7e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
vlsseg7e8.v v8, (a0), a1
# CHECK-INST: vlsseg7e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
vlsseg7e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
vlsseg7e16.v v8, (a0), a1
# CHECK-INST: vlsseg7e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
vlsseg7e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
vlsseg7e32.v v8, (a0), a1
# CHECK-INST: vlsseg7e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
vlsseg7e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
vlsseg7e64.v v8, (a0), a1
# CHECK-INST: vlsseg7e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
vluxseg7ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 c4 <unknown>
vluxseg7ei8.v v8, (a0), v4
# CHECK-INST: vluxseg7ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 c6 <unknown>
vluxseg7ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 c4 <unknown>
vluxseg7ei16.v v8, (a0), v4
# CHECK-INST: vluxseg7ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 c6 <unknown>
vluxseg7ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 c4 <unknown>
vluxseg7ei32.v v8, (a0), v4
# CHECK-INST: vluxseg7ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 c6 <unknown>
vluxseg7ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 c4 <unknown>
vluxseg7ei64.v v8, (a0), v4
# CHECK-INST: vluxseg7ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 c6 <unknown>
vloxseg7ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 cc <unknown>
vloxseg7ei8.v v8, (a0), v4
# CHECK-INST: vloxseg7ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 ce <unknown>
vloxseg7ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 cc <unknown>
vloxseg7ei16.v v8, (a0), v4
# CHECK-INST: vloxseg7ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 ce <unknown>
vloxseg7ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 cc <unknown>
vloxseg7ei32.v v8, (a0), v4
# CHECK-INST: vloxseg7ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 ce <unknown>
vloxseg7ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 cc <unknown>
vloxseg7ei64.v v8, (a0), v4
# CHECK-INST: vloxseg7ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 ce <unknown>
vlseg8e8.v v8, (a0), v0.t
# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
vlseg8e8.v v8, (a0)
# CHECK-INST: vlseg8e8.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
vlseg8e16.v v8, (a0), v0.t
# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
vlseg8e16.v v8, (a0)
# CHECK-INST: vlseg8e16.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
vlseg8e32.v v8, (a0), v0.t
# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
vlseg8e32.v v8, (a0)
# CHECK-INST: vlseg8e32.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
vlseg8e64.v v8, (a0), v0.t
# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
vlseg8e64.v v8, (a0)
# CHECK-INST: vlseg8e64.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
vlseg8e8ff.v v8, (a0), v0.t
# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
vlseg8e8ff.v v8, (a0)
# CHECK-INST: vlseg8e8ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 05 e3 <unknown>
vlseg8e16ff.v v8, (a0), v0.t
# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
vlseg8e16ff.v v8, (a0)
# CHECK-INST: vlseg8e16ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 05 e3 <unknown>
vlseg8e32ff.v v8, (a0), v0.t
# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
vlseg8e32ff.v v8, (a0)
# CHECK-INST: vlseg8e32ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 05 e3 <unknown>
vlseg8e64ff.v v8, (a0), v0.t
# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
vlseg8e64ff.v v8, (a0)
# CHECK-INST: vlseg8e64ff.v v8, (a0)
# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 05 e3 <unknown>
vlsseg8e8.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
vlsseg8e8.v v8, (a0), a1
# CHECK-INST: vlsseg8e8.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
vlsseg8e16.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
vlsseg8e16.v v8, (a0), a1
# CHECK-INST: vlsseg8e16.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
vlsseg8e32.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
vlsseg8e32.v v8, (a0), a1
# CHECK-INST: vlsseg8e32.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
vlsseg8e64.v v8, (a0), a1, v0.t
# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
vlsseg8e64.v v8, (a0), a1
# CHECK-INST: vlsseg8e64.v v8, (a0), a1
# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
vluxseg8ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 e4 <unknown>
vluxseg8ei8.v v8, (a0), v4
# CHECK-INST: vluxseg8ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 e6 <unknown>
vluxseg8ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 e4 <unknown>
vluxseg8ei16.v v8, (a0), v4
# CHECK-INST: vluxseg8ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 e6 <unknown>
vluxseg8ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 e4 <unknown>
vluxseg8ei32.v v8, (a0), v4
# CHECK-INST: vluxseg8ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 e6 <unknown>
vluxseg8ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 e4 <unknown>
vluxseg8ei64.v v8, (a0), v4
# CHECK-INST: vluxseg8ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 e6 <unknown>
vloxseg8ei8.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 ec <unknown>
vloxseg8ei8.v v8, (a0), v4
# CHECK-INST: vloxseg8ei8.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 04 45 ee <unknown>
vloxseg8ei16.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 ec <unknown>
vloxseg8ei16.v v8, (a0), v4
# CHECK-INST: vloxseg8ei16.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 54 45 ee <unknown>
vloxseg8ei32.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 ec <unknown>
vloxseg8ei32.v v8, (a0), v4
# CHECK-INST: vloxseg8ei32.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 64 45 ee <unknown>
vloxseg8ei64.v v8, (a0), v4, v0.t
# CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t
# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 ec <unknown>
vloxseg8ei64.v v8, (a0), v4
# CHECK-INST: vloxseg8ei64.v v8, (a0), v4
# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 07 74 45 ee <unknown>
vsseg2e8.v v24, (a0), v0.t
# CHECK-INST: vsseg2e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 20 <unknown>
vsseg2e8.v v24, (a0)
# CHECK-INST: vsseg2e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
vsseg2e16.v v24, (a0), v0.t
# CHECK-INST: vsseg2e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 20 <unknown>
vsseg2e16.v v24, (a0)
# CHECK-INST: vsseg2e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
vsseg2e32.v v24, (a0), v0.t
# CHECK-INST: vsseg2e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 20 <unknown>
vsseg2e32.v v24, (a0)
# CHECK-INST: vsseg2e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
vsseg2e64.v v24, (a0), v0.t
# CHECK-INST: vsseg2e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 20 <unknown>
vsseg2e64.v v24, (a0)
# CHECK-INST: vsseg2e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
vssseg2e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 28 <unknown>
vssseg2e8.v v24, (a0), a1
# CHECK-INST: vssseg2e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 2a <unknown>
vssseg2e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 28 <unknown>
vssseg2e16.v v24, (a0), a1
# CHECK-INST: vssseg2e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 2a <unknown>
vssseg2e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 28 <unknown>
vssseg2e32.v v24, (a0), a1
# CHECK-INST: vssseg2e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 2a <unknown>
vssseg2e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 28 <unknown>
vssseg2e64.v v24, (a0), a1
# CHECK-INST: vssseg2e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 2a <unknown>
vsuxseg2ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 24 <unknown>
vsuxseg2ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg2ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 26 <unknown>
vsuxseg2ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 24 <unknown>
vsuxseg2ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg2ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 26 <unknown>
vsuxseg2ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 24 <unknown>
vsuxseg2ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg2ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 26 <unknown>
vsuxseg2ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x24]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 24 <unknown>
vsuxseg2ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg2ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x26]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 26 <unknown>
vsoxseg2ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
vsoxseg2ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg2ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
vsoxseg2ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
vsoxseg2ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg2ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
vsoxseg2ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
vsoxseg2ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg2ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
vsoxseg2ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
vsoxseg2ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg2ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
vsseg3e8.v v24, (a0), v0.t
# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
vsseg3e8.v v24, (a0)
# CHECK-INST: vsseg3e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
vsseg3e16.v v24, (a0), v0.t
# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
vsseg3e16.v v24, (a0)
# CHECK-INST: vsseg3e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
vsseg3e32.v v24, (a0), v0.t
# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
vsseg3e32.v v24, (a0)
# CHECK-INST: vsseg3e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
vsseg3e64.v v24, (a0), v0.t
# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
vsseg3e64.v v24, (a0)
# CHECK-INST: vsseg3e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
vssseg3e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 48 <unknown>
vssseg3e8.v v24, (a0), a1
# CHECK-INST: vssseg3e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 4a <unknown>
vssseg3e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 48 <unknown>
vssseg3e16.v v24, (a0), a1
# CHECK-INST: vssseg3e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 4a <unknown>
vssseg3e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 48 <unknown>
vssseg3e32.v v24, (a0), a1
# CHECK-INST: vssseg3e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 4a <unknown>
vssseg3e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 48 <unknown>
vssseg3e64.v v24, (a0), a1
# CHECK-INST: vssseg3e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 4a <unknown>
vsuxseg3ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 44 <unknown>
vsuxseg3ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg3ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 46 <unknown>
vsuxseg3ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 44 <unknown>
vsuxseg3ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg3ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 46 <unknown>
vsuxseg3ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 44 <unknown>
vsuxseg3ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg3ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 46 <unknown>
vsuxseg3ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x44]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 44 <unknown>
vsuxseg3ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg3ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x46]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 46 <unknown>
vsoxseg3ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
vsoxseg3ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg3ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
vsoxseg3ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
vsoxseg3ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg3ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
vsoxseg3ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
vsoxseg3ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg3ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
vsoxseg3ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
vsoxseg3ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg3ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
vsseg4e8.v v24, (a0), v0.t
# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
vsseg4e8.v v24, (a0)
# CHECK-INST: vsseg4e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
vsseg4e16.v v24, (a0), v0.t
# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
vsseg4e16.v v24, (a0)
# CHECK-INST: vsseg4e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
vsseg4e32.v v24, (a0), v0.t
# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
vsseg4e32.v v24, (a0)
# CHECK-INST: vsseg4e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
vsseg4e64.v v24, (a0), v0.t
# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
vsseg4e64.v v24, (a0)
# CHECK-INST: vsseg4e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
vssseg4e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 68 <unknown>
vssseg4e8.v v24, (a0), a1
# CHECK-INST: vssseg4e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 6a <unknown>
vssseg4e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 68 <unknown>
vssseg4e16.v v24, (a0), a1
# CHECK-INST: vssseg4e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 6a <unknown>
vssseg4e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 68 <unknown>
vssseg4e32.v v24, (a0), a1
# CHECK-INST: vssseg4e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 6a <unknown>
vssseg4e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 68 <unknown>
vssseg4e64.v v24, (a0), a1
# CHECK-INST: vssseg4e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 6a <unknown>
vsuxseg4ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 64 <unknown>
vsuxseg4ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg4ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 66 <unknown>
vsuxseg4ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 64 <unknown>
vsuxseg4ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg4ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 66 <unknown>
vsuxseg4ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 64 <unknown>
vsuxseg4ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg4ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 66 <unknown>
vsuxseg4ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x64]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 64 <unknown>
vsuxseg4ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg4ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x66]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 66 <unknown>
vsoxseg4ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
vsoxseg4ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg4ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
vsoxseg4ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
vsoxseg4ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg4ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
vsoxseg4ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
vsoxseg4ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg4ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
vsoxseg4ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
vsoxseg4ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg4ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
vsseg5e8.v v24, (a0), v0.t
# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
vsseg5e8.v v24, (a0)
# CHECK-INST: vsseg5e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
vsseg5e16.v v24, (a0), v0.t
# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
vsseg5e16.v v24, (a0)
# CHECK-INST: vsseg5e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
vsseg5e32.v v24, (a0), v0.t
# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
vsseg5e32.v v24, (a0)
# CHECK-INST: vsseg5e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
vsseg5e64.v v24, (a0), v0.t
# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
vsseg5e64.v v24, (a0)
# CHECK-INST: vsseg5e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
vssseg5e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 88 <unknown>
vssseg5e8.v v24, (a0), a1
# CHECK-INST: vssseg5e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
vssseg5e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 88 <unknown>
vssseg5e16.v v24, (a0), a1
# CHECK-INST: vssseg5e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
vssseg5e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 88 <unknown>
vssseg5e32.v v24, (a0), a1
# CHECK-INST: vssseg5e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
vssseg5e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x88]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 88 <unknown>
vssseg5e64.v v24, (a0), a1
# CHECK-INST: vssseg5e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
vsuxseg5ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 84 <unknown>
vsuxseg5ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg5ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 86 <unknown>
vsuxseg5ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 84 <unknown>
vsuxseg5ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg5ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 86 <unknown>
vsuxseg5ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 84 <unknown>
vsuxseg5ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg5ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 86 <unknown>
vsuxseg5ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 84 <unknown>
vsuxseg5ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg5ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 86 <unknown>
vsoxseg5ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
vsoxseg5ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg5ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
vsoxseg5ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
vsoxseg5ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg5ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
vsoxseg5ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
vsoxseg5ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg5ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
vsoxseg5ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
vsoxseg5ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg5ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
vsseg6e8.v v24, (a0), v0.t
# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
vsseg6e8.v v24, (a0)
# CHECK-INST: vsseg6e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
vsseg6e16.v v24, (a0), v0.t
# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
vsseg6e16.v v24, (a0)
# CHECK-INST: vsseg6e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
vsseg6e32.v v24, (a0), v0.t
# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
vsseg6e32.v v24, (a0)
# CHECK-INST: vsseg6e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
vsseg6e64.v v24, (a0), v0.t
# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
vsseg6e64.v v24, (a0)
# CHECK-INST: vsseg6e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
vssseg6e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 a8 <unknown>
vssseg6e8.v v24, (a0), a1
# CHECK-INST: vssseg6e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 aa <unknown>
vssseg6e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 a8 <unknown>
vssseg6e16.v v24, (a0), a1
# CHECK-INST: vssseg6e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
vssseg6e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 a8 <unknown>
vssseg6e32.v v24, (a0), a1
# CHECK-INST: vssseg6e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
vssseg6e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 a8 <unknown>
vssseg6e64.v v24, (a0), a1
# CHECK-INST: vssseg6e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
vsuxseg6ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 a4 <unknown>
vsuxseg6ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg6ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 a6 <unknown>
vsuxseg6ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 a4 <unknown>
vsuxseg6ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg6ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 a6 <unknown>
vsuxseg6ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 a4 <unknown>
vsuxseg6ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg6ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 a6 <unknown>
vsuxseg6ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xa4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 a4 <unknown>
vsuxseg6ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg6ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xa6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 a6 <unknown>
vsoxseg6ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
vsoxseg6ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg6ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
vsoxseg6ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
vsoxseg6ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg6ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
vsoxseg6ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
vsoxseg6ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg6ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
vsoxseg6ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
vsoxseg6ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg6ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
vsseg7e8.v v24, (a0), v0.t
# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
vsseg7e8.v v24, (a0)
# CHECK-INST: vsseg7e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
vsseg7e16.v v24, (a0), v0.t
# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
vsseg7e16.v v24, (a0)
# CHECK-INST: vsseg7e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
vsseg7e32.v v24, (a0), v0.t
# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
vsseg7e32.v v24, (a0)
# CHECK-INST: vsseg7e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
vsseg7e64.v v24, (a0), v0.t
# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
vsseg7e64.v v24, (a0)
# CHECK-INST: vsseg7e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
vssseg7e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 c8 <unknown>
vssseg7e8.v v24, (a0), a1
# CHECK-INST: vssseg7e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 ca <unknown>
vssseg7e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 c8 <unknown>
vssseg7e16.v v24, (a0), a1
# CHECK-INST: vssseg7e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 ca <unknown>
vssseg7e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 c8 <unknown>
vssseg7e32.v v24, (a0), a1
# CHECK-INST: vssseg7e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 ca <unknown>
vssseg7e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 c8 <unknown>
vssseg7e64.v v24, (a0), a1
# CHECK-INST: vssseg7e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 ca <unknown>
vsuxseg7ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 c4 <unknown>
vsuxseg7ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg7ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 c6 <unknown>
vsuxseg7ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 c4 <unknown>
vsuxseg7ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg7ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 c6 <unknown>
vsuxseg7ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 c4 <unknown>
vsuxseg7ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg7ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 c6 <unknown>
vsuxseg7ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xc4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 c4 <unknown>
vsuxseg7ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg7ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xc6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 c6 <unknown>
vsoxseg7ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
vsoxseg7ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg7ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
vsoxseg7ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
vsoxseg7ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg7ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
vsoxseg7ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
vsoxseg7ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg7ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
vsoxseg7ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
vsoxseg7ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg7ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
vsseg8e8.v v24, (a0), v0.t
# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
vsseg8e8.v v24, (a0)
# CHECK-INST: vsseg8e8.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
vsseg8e16.v v24, (a0), v0.t
# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
vsseg8e16.v v24, (a0)
# CHECK-INST: vsseg8e16.v v24, (a0)
# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
vsseg8e32.v v24, (a0), v0.t
# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
vsseg8e32.v v24, (a0)
# CHECK-INST: vsseg8e32.v v24, (a0)
# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
vsseg8e64.v v24, (a0), v0.t
# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
vsseg8e64.v v24, (a0)
# CHECK-INST: vsseg8e64.v v24, (a0)
# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
vssseg8e8.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 e8 <unknown>
vssseg8e8.v v24, (a0), a1
# CHECK-INST: vssseg8e8.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
vssseg8e16.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 e8 <unknown>
vssseg8e16.v v24, (a0), a1
# CHECK-INST: vssseg8e16.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
vssseg8e32.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 e8 <unknown>
vssseg8e32.v v24, (a0), a1
# CHECK-INST: vssseg8e32.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
vssseg8e64.v v24, (a0), a1, v0.t
# CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 e8 <unknown>
vssseg8e64.v v24, (a0), a1
# CHECK-INST: vssseg8e64.v v24, (a0), a1
# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
vsuxseg8ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 e4 <unknown>
vsuxseg8ei8.v v24, (a0), v4
# CHECK-INST: vsuxseg8ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 e6 <unknown>
vsuxseg8ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 e4 <unknown>
vsuxseg8ei16.v v24, (a0), v4
# CHECK-INST: vsuxseg8ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 e6 <unknown>
vsuxseg8ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 e4 <unknown>
vsuxseg8ei32.v v24, (a0), v4
# CHECK-INST: vsuxseg8ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 e6 <unknown>
vsuxseg8ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xe4]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 e4 <unknown>
vsuxseg8ei64.v v24, (a0), v4
# CHECK-INST: vsuxseg8ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xe6]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 e6 <unknown>
vsoxseg8ei8.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
vsoxseg8ei8.v v24, (a0), v4
# CHECK-INST: vsoxseg8ei8.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x0c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 0c 45 ee <unknown>
vsoxseg8ei16.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x5c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 ec <unknown>
vsoxseg8ei16.v v24, (a0), v4
# CHECK-INST: vsoxseg8ei16.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
vsoxseg8ei32.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x6c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 ec <unknown>
vsoxseg8ei32.v v24, (a0), v4
# CHECK-INST: vsoxseg8ei32.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
vsoxseg8ei64.v v24, (a0), v4, v0.t
# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t
# CHECK-ENCODING: [0x27,0x7c,0x45,0xec]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 ec <unknown>
vsoxseg8ei64.v v24, (a0), v4
# CHECK-INST: vsoxseg8ei64.v v24, (a0), v4
# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
-# CHECK-ERROR: instruction requires the following: 'Zvlsseg'
+# CHECK-ERROR: instruction requires the following: 'V'
# CHECK-UNKNOWN: 27 7c 45 ee <unknown>
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