[PATCH] D112408: [RISCV] Add the zve extension according to the v1.0 spec

[Shao-Ce SUN via Phabricator via cfe-commits]

achieveartificialintelligence added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
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Do we need `+f` here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112408/new/

https://reviews.llvm.org/D112408