[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

Few more grep result (by `grep zvlsseg  * -Rin`), I think should remove:

  clang/include/clang/Basic/riscv_vector.td:218:  // Sub extension of vector spec. Currently only support Zvlsseg.
  clang/include/clang/Basic/riscv_vector.td:221:  // Number of fields for Zvlsseg.
  clang/include/clang/Basic/riscv_vector.td:1570:let RequiredExtensions = ["Zvlsseg"] in {

We've some predictor named with `zvlsseg` like `IsZvlsseg` and `isRVVSpillForZvlsseg`, maybe rename to `SegmentVectorRegister` or `VectorRegisterGroup`?

Optional, nice to rename:

  clang/include/clang/Basic/RISCVVTypes.def:33:// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:293:  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:294:  if (!ZvlssegInfo)
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:296:  unsigned NF = ZvlssegInfo->first;
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:297:  unsigned LMUL = ZvlssegInfo->second;
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:338:  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MBBI->getOpcode());
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:339:  if (!ZvlssegInfo)
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:341:  unsigned NF = ZvlssegInfo->first;
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:342:  unsigned LMUL = ZvlssegInfo->second;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:222:          // FIXME: The COPY of subregister of Zvlsseg register will not be able
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:458:  bool IsZvlsseg = true;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:474:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:477:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:480:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:483:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:519:    if (IsZvlsseg) {
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:520:      // For spilling/reloading Zvlsseg registers, append the dummy field for
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:552:  bool IsZvlsseg = true;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:568:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:571:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:574:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:577:    IsZvlsseg = false;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:612:    if (IsZvlsseg) {
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:613:      // For spilling/reloading Zvlsseg registers, append the dummy field for
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1051:    unsigned NF = isRVVSpillForZvlsseg(Opcode)->first;
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1880:      !isRVVWholeLoadStore(Opcode) && !isRVVSpillForZvlsseg(Opcode))
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1888:RISCVInstrInfo::isRVVSpillForZvlsseg(unsigned Opcode) const {
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:273:  auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MI.getOpcode());
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:274:  if (ZvlssegInfo) {
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:277:    uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:282:    // The last argument of pseudo spilling opcode for zvlsseg is the length of
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:283:    // one element of zvlsseg types. For example, for vint32m2x2_t, it will be
  llvm/lib/Target/RISCV/RISCVInstrInfo.h:178:  isRVVSpillForZvlsseg(unsigned Opcode) const;


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