[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension
Craig Topper via Phabricator via cfe-commits
cfe-commits at lists.llvm.org
Tue Jan 18 08:50:24 PST 2022
craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4246
+ case Intrinsic::riscv_fsl:
+ return DAG.getNode(RISCVISD::FSL, DL, XLenVT, Op.getOperand(1),
+ Op.getOperand(2), Op.getOperand(3));
The operand order for RISCVISD::FSL/FSR match llvm.fshl and llvm.fshr rather than rs1, rs2, rs3 order. I think the operand order you want for riscv.fsl and riscv.fsr should be rs1, rs2, rs3.
And the assembly printing for fsl/fsr prints $rd, $rs1, $rs3, $rs2 makes this even more confusing.
I'll put up a patch to change RISCVISD::FSL/FSR and RISCVISD::FSLW/FSRW order to be in rs1, rs2, rs3 order.
rG LLVM Github Monorepo
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